Non-Volatile Storage Systems with Go To Sleep Adaption

• US 20130151755A1
• Filed: 12/12/2011
• Published: 06/13/2013
• Est. Priority Date: 12/12/2011
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Elhamias, Reuven, Fishler, Ram
• Application Number:
  US13/323,612
• Publication Number:
  US 20130151755A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a host resettable parameter file. In other embodiments, the memory system monitors the time between host commands and adjusts this delay automatically.

Claims

13. A non-volatile memory system, comprising:

a non-volatile memory circuit; and

a controller circuit connected to non-volatile memory circuit, where the controller circuit manages the transfer of data between the memory circuit and a host to which the memory system is connected and the storage of the data on the memory system, the controller circuit including logic circuitry and a volatile random access memory,

wherein, in response to the memory system not receiving a host command within in a period of time specified by a delay parameter, the controller places the memory system into a low-power standby mode,

wherein the controller maintains a first value for the delay parameter in the non-volatile memory circuit, and

wherein the controller resets the value of the delay parameter in response to a command that specifies a value for the delay parameter different than the first value.

14. The non-volatile memory of claim 13, wherein the memory system transfers the first value for the delay parameter to the volatile random access memory upon initialization.

15. The non-volatile memory of claim 14, wherein the controller resets the value of the delay parameter in the volatile random access memory in response to said command.

16. The non-volatile memory of claim 15, wherein the controller further resets the first value in response to said command.

17. The non-volatile memory of claim 13, wherein, in response to the memory system said command while in the low-power standby mode, the controller places the memory system into a standard operating mode and subsequently executes the command and resets the value of the delay parameter.

18. The non-volatile memory of claim 13, wherein the controller maintains a maximum value to which the delay parameter may be set in the non-volatile memory circuit.

19. The non-volatile memory of claim 13, wherein, in response a subsequent command, the controller further resets the value of the delay parameter.

20. The non-volatile memory of claim 13, wherein the low-power standby mode differs from a standard mode in which the memory system can execute host command in that the low-power standby mode includes turning off power to the memory circuit.

21. The non-volatile memory of claim 13, wherein the low-power standby mode differs from a standard mode in which the memory system can execute host command in that the low-power standby mode includes turning off a clock circuit of the memory system.

22. The non-volatile memory of claim 13, wherein the low-power standby mode differs from a standard mode in which the memory system can execute host command in that the low-power standby mode includes turning off power to portions of the controller circuit.

23. A method of operating a non-volatile memory system, the memory system including a non-volatile memory circuit and a controller circuit for managing data stored in the non-volatile memory circuit and the interactions between the memory system and a host to which the memory system is connected, wherein the controller circuit operates the memory system in one of either a standard mode or a low-power standby mode, and wherein the memory system executes commands from the host in the standard mode and lapses from the standard mode into the low-power standby mode after a delay value unless receiving a further command from the host prior to lapsing into the standby mode, the method comprising:

monitoring by the controller of a plurality of commands from the host to the memory system;

based on said monitoring, determining the time between the commands; and

optimizing by the controller of the delay value based on the time between the commands.

24. The method of claim 23, wherein the plurality of commands includes a first command and a second command, the second command being the first subsequent command received by memory system after the first command, wherein said optimizing includes:

in response to receiving the second command while in the standard mode, shortening the delay value.

25. The method of claim 24, wherein shortening the delay includes setting the delay value to be intermediate to the current delay value and the time between the first and second commands.

26. The method of claim 23, wherein the plurality of commands includes a first command and a second command, the second command being the first subsequent command received by memory system after the first command, wherein said optimizing includes:

in response to receiving the second command while in the standby mode, reverting to the standard mode; and

once in the standard mode, executing the second command and lengthening the delay value.

27. The method of claim 26, wherein lengthening the delay includes setting the delay value to be intermediate to the current delay value and a maximum delay value.

28. The method of claim 27, wherein said maximum delay value is a settable parameter for the memory system.

29. The method of claim 27, wherein lengthening the delay includes setting the delay value to be increased by a fraction of the difference between the current delay value and the maximum delay value

30. The method of claim 29, wherein the fraction is a settable parameter for the memory system.

31. The method of claim 29, wherein the fraction is dynamically determined by the controller circuit.

32. The method of claim 23, wherein operating in the low-power standby mode includes turning off power to the memory circuit.

33. The method of claim 23, wherein operating in the low-power standby mode includes turning off a clock circuit of the memory system.

34. The method of claim 23, wherein operating in the low-power standby mode includes turning off power to portions of the controller circuit.

35-1. The method of claim 35, wherein the memory system transfers a copy of the delay value from the non-volatile memory to volatile memory on the controller circuit at initialization.