Multi-Chip Initialization Using a Parallel Firmware Boot Process

• US 20130151829A1
• Filed: 12/08/2011
• Published: 06/13/2013
• Est. Priority Date: 12/08/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Amann, Eberhard, Haverkamp, Frank, Huth, Thomas, Kunigk, Jan
• Granted Patent: US 8,954,721 B2
• Time in Patent Office: Days
• US Class Current: 713/2
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files

Abstract

Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

Claims

1. A method, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system, comprising:

performing, in parallel, a multi-chip agnostic isolated boot phase operation to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system;

performing, in parallel, a multi-chip aware isolated boot phase operation of each of the processor chips where each of the processor chips has its own separately configured physical address space; and

performing a unified configuration phase operation to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

2. The method of claim 1, wherein performing a multi-chip agnostic isolated boot phase operation comprises:

initializing a chip identifier of each of the processor chips in the plurality of processor chips to have a same master chip identifier; and

setting a virtual to physical address mapping structure of a memory management unit of each of the processor chips such that for each pair of virtual address and physical address, the virtual address is the same as the physical address.

3. The method of claim 1, wherein, during the multi-chip agnostic isolated boot phase operation, the initial boot of each of the plurality of processor chips is performed by executing boot code from a shared flash memory that is shared by all of the processor chips in the plurality of processor chips.

4. The method of claim 1, wherein performing a multi-chip agnostic isolated boot phase operation comprises reading, by each processor chip in the plurality of processor chips, a unique chip identifier for the processor chip from a boot-assist-logic shared by the processor chips, and wherein the boot-assist-logic provides an interface for each of the processor chips to access the boot code in the flash memory.

5. The method of claim 4, wherein the unique chip identifier for a processor chip in the plurality of processor chips is a port number associated with a port of the boot-assist-logic to which the processor chip is coupled.

6. The method of claim 4, wherein the unique chip identifier for the processor chip in the plurality of processor chips is derived based on an order in which arbitration for a semaphore is won amongst the plurality of chips, and wherein the semaphore protects access to a shared storage location.

7. The method of claim 4, wherein performing a multi-chip aware isolated boot phase operation of each of the processor chips where each of the processor chips has its own separately configured physical address space comprises:

reconfiguring a virtual to real address mapping of each of the processor chips based on a corresponding chip identifier of the processor chip such that each processor chip has its own separately configured address space.

8. The method of claim 7, wherein performing the multi-chip aware isolated boot phase operation further comprises:

moving boot code from a flash memory from which the boot code was being executed as part of the multi-chip agnostic isolated boot phase operation into the separately configured address spaces of each of the processor chips; and

continuing execution of the boot code in each of the processor chips from the separate configured address spaces of the processor chips.

9. The method of claim 1, wherein performing a unified configuration phase operation to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip comprises:

stopping execution of code on the slave processor chips;

reconfiguring a virtual to address mapping of the slave processor chips to map virtual addresses to physical addresses of a memory of the master processor chip; and

executing, by the slave processor chips, code from the memory of the master processor chip using the reconfigured virtual to address mappings of the slave processor chips.

10. The method of claim 1, wherein separate system configuration table data structures are generated for each of the processor chips in the plurality of processor chips during the multi-chip agnostic isolated boot phase operation and multi-chip aware isolated boot phase operation, and wherein performing a unified configuration phase operation further comprises merging the separate system configuration table data structures of each of the processor chips into a single merged system configuration table data structure, and providing the single merged system configuration table data structure to an operating system of the multi-chip data processing system for use in managing devices of the multi-chip data processing system.

11. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a multi-chip data processing system, causes the multi-chip data processing system to:

perform, in parallel, a multi-chip agnostic isolated boot phase operation to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system;

perform, in parallel, a multi-chip aware isolated boot phase operation of each of the processor chips where each of the processor chips has its own separately configured physical address space; and

perform a unified configuration phase operation to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

12. The computer program product of claim 11, wherein performing a multi-chip agnostic isolated boot phase operation comprises:

initializing a chip identifier of each of the processor chips in the plurality of processor chips to have a same master chip identifier; and

setting a virtual to physical address mapping structure of a memory management unit of each of the processor chips such that for each pair of virtual address and physical address, the virtual address is the same as the physical address.

13. The computer program product of claim 11, wherein, during the multi-chip agnostic isolated boot phase operation, the initial boot of each of the plurality of processor chips is performed by executing boot code from a shared flash memory that is shared by all of the processor chips in the plurality of processor chips.

14. The computer program product of claim 11, wherein performing a multi-chip agnostic isolated boot phase operation comprises reading, by each processor chip in the plurality of processor chips, a unique chip identifier for the processor chip from a boot-assist-logic shared by the processor chips, and wherein the boot-assist-logic provides an interface for each of the processor chips to access the boot code in the flash memory.

15. The computer program product of claim 14, wherein the unique chip identifier for a processor chip in the plurality of processor chips is a port number associated with a port of the boot-assist-logic to which the processor chip is coupled.

16. The computer program product of claim 14, wherein the unique chip identifier for the processor chip in the plurality of processor chips is derived based on an order in which arbitration for a semaphore is won amongst the plurality of chips, and wherein the semaphore protects access to a shared storage location.

17. The computer program product of claim 14, wherein performing a multi-chip aware isolated boot phase operation of each of the processor chips where each of the processor chips has its own separately configured address space comprises:

reconfiguring a virtual to real address mapping of each of the processor chips based on a corresponding chip identifier of the processor chip such that each processor chip has its own separately configured address space.

18. The computer program product of claim 17, wherein performing the multi-chip aware isolated boot phase operation further comprises:

moving boot code from a flash memory from which the boot code was being executed as part of the multi-chip agnostic isolated boot phase operation into the separately configured address spaces of each of the processor chips; and

continuing execution of the boot code in each of the processor chips from the separate configured address spaces of the processor chips.

19. The computer program product of claim 11, wherein performing a unified configuration phase operation to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip comprises:

stopping execution of code on the slave processor chips;

reconfiguring a virtual to address mapping of the slave processor chips to map virtual addresses to physical addresses of a memory of the master processor chip; and

executing, by the slave processor chips, code from the memory of the master processor chip using the reconfigured virtual to address mappings of the slave processor chips.

20. The computer program product of claim 11, wherein separate system configuration table data structures are generated for each of the processor chips in the plurality of processor chips during the multi-chip agnostic isolated boot phase operation and multi-chip aware isolated boot phase operation, and wherein performing a unified configuration phase operation further comprises merging the separate system configuration table data structures of each of the processor chips into a single merged system configuration table data structure, and providing the single merged system configuration table data structure to an operating system of the multi-chip data processing system for use in managing devices of the multi-chip data processing system.

21. An apparatus, comprising:

a plurality of processor chips; and

a shared memory comprising boot code for performing an initial boot operation of the plurality of processor chips, wherein the plurality of processor chips comprise logic to cause the processor chips to;

perform, in parallel, using the boot code in the shared memory, a multi-chip agnostic isolated boot phase operation to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system;

perform, in parallel, a multi-chip aware isolated boot phase operation of each of the processor chips where each of the processor chips has its own separately configured physical address space; and

perform a unified configuration phase operation to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.