Power Management IC Having a Power Supply PWM that is Controllable Using Either an Analog or a Digital Feedback Path

• US 20130151871A1
• Filed: 05/01/2012
• Published: 06/13/2013
• Est. Priority Date: 12/08/2011
• Status: Active Grant

• Current Assignee: Active-Semi, Inc. (Qorvo, Inc.)
• Original Assignee: Active-Semi, Inc. (Qorvo, Inc.)
• Inventors: Huynh, Steven
• Granted Patent: US 8,898,491 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level

Abstract

A Power Management Integrated Circuit (PMIC) includes a pulse width modulator and driver circuit (PWMDC), a processor, and high-side and low-side driver circuitry. The PWMDC, along with components external to the PMIC, forms a switching power supply. A small linear regulator powers the PWMDC from power received via a terminal. The power supply supplies power to other on-chip circuitry, including the driver circuitry and processor. The PWMDC starts an on pulse (of a power supply switching cycle) in response to a clock signal. In a first mode, the PWMDC stops the on pulse based on a signal received from a terminal via an analog feedback signal path. In a second mode, the PWMDC stops the on pulse based on a signal received via a digital feedback signal path. In one example, the digital feedback signal path extends from a terminal, through an ADC, processor, and DAC, to an error node.

Claims

1. An integrated circuit comprising:

a digital processor that executes instructions;

a first sense input terminal;

a second sense input terminal;

a driver output terminal; and

a pulse width modulator and driver circuit (PWMDC) that starts an on pulse by driving a control signal on the driver output terminal to a first voltage level in response to an edge of a clock signal, and in a first mode stops the on pulse by driving the control signal on the driver output terminal to a second voltage level when a first signal on the first sense input terminal has a predetermined relationship with respect to an error signal derived from a second signal on the second sense input terminal, and in a second mode stops the on pulse by driving the control signal on the driver output terminal to the second voltage level when the first signal on the first sense input terminal has a predetermined relationship with respect to a multi-bit digital value received from the digital processor.

2. The integrated circuit of claim 1, wherein in the second mode the digital processor operates as part of a digital feedback signal path, and wherein the digital feedback path extends through an Analog-to-Digital Converter (ADC), through the digital processor, and to the PWMDC.

3. The integrated circuit of claim 2, wherein in the second mode the digital processor operates as part of the digital feedback signal path by repeatedly changing the multi-bit digital value supplied to the PWMDC.

4. The integrated circuit of claim 1, wherein the digital processor controls whether the PWMDC operates in the first mode or in the second mode.

5. The integrated circuit of claim 1, wherein the PWMDC includes a comparator, and wherein a first analog signal path extends from the first sense input terminal and to a first input lead of the comparator.

6. The integrated circuit of claim 5, wherein the PWMDC includes an error node, and wherein in the first mode a second analog signal path extends from the second sense input terminal, through an error amplifier of the PWMDC, and to the error node.

7. The integrated circuit of claim 6, wherein the error node is a second input lead of the comparator.

8. The integrated circuit of claim 1, wherein the PWMDC includes an error node, and wherein in the second mode the multi-bit digital value received from the digital processor results in a voltage on the error node being clamped to a voltage that corresponds to the multi-bit digital value.

9. The integrated circuit of claim 6, wherein the second analog signal path has a gain, and wherein the gain of the second analog signal feedback path is programmable by the digital processor.

10. The integrated circuit of claim 1, wherein the PWMDC includes an on-chip oscillator that has no off-chip components, and wherein the on-chip oscillator outputs the clock signal.

11. The integrated circuit of claim 1, further comprising:

a third input terminal; and

linear regulator circuitry that converts a voltage present on the third input terminal into a regulated supply voltage, and wherein the regulated supply voltage powers the PWMDC but does not power the digital processor.

12. The integrated circuit of claim 1, further comprising:

an Analog-to-Digital Converter (ADC), wherein in the second mode the digital processor receives information from the ADC and based at least in part on the information changes the multi-bit digital value.

13. The integrated circuit of claim 1, wherein the PWMDC is adapted to be a part of a switching power supply, wherein the switching power supply includes the PWMDC and components external to the integrated circuit, and wherein the switching power supply generates a supply voltage present on the second sense terminal.

14. The integrated circuit of claim 1, wherein a control electrode of a power transistor is coupled to the driver output terminal, wherein the power transistor is external to the integrated circuit, and wherein the on pulse results in the power transistor being pulsed on.

15. The integrated circuit of claim 1, further comprising:

high-side driver and low-side driver circuitry, wherein the PWMDC is adapted to be a part of a switching power supply, wherein the switching power supply includes the PWMDC and components external to the integrated circuit, and wherein at least some of the high-side driver and low-side driver circuitry is powered by the switching power supply.

16. The integrated circuit of claim 15, further comprising:

linear regulator circuitry that receives a voltage from the switching power supply and that supplies a regulated supply voltage to the digital processor.

17. A method comprising:

providing a digital processor as part of an integrated circuit, wherein the digital processor executes instructions; and

providing a pulse width modulator and driver circuit (PWMDC) on the integrated circuit, wherein in a first mode an error signal on an error node within the PWMDC is supplied by an analog feedback signal path, wherein the analog feedback signal path extends from an input sense terminal of the integrated circuit and through an error amplifier of the PWMDC, and to the error node, and wherein in a second mode the error signal on the error node within the PWMDC is supplied by a digital feedback signal path, wherein the digital feedback signal path extends through the digital processor and through a Digital-to-Analog Converter (DAC) and to the error node.

18. The method of claim 17, further comprising:

providing high-side driver and low-side driver circuitry on the integrated circuit, wherein the PWMDC is adapted to be a part of a switching power supply, wherein the switching power supply includes the PWMDC and components external to the integrated circuit, and wherein at least some of the high-side driver and low-side driver circuitry is powered by the switching power supply.

19. The method of claim 18, further comprising:

providing linear regulator circuitry on the integrated circuit, wherein the linear regulator circuitry converts a voltage present on a terminal of the integrated circuit into a regulated supply voltage, and wherein the regulated supply voltage powers the PWMDC but does not power the high-side drive and low-side driver circuitry and does not power the digital processor.

20. An integrated circuit comprising:

a digital processor adapted to execute instructions;

a first terminal;

a second terminal;

means for pulse width modulating a switching power supply so as to generate a supply voltage, wherein the means is for starting an on pulse by driving a control signal on the first terminal to a first voltage level, and in a first mode is for stopping the on pulse by driving the control signal to a second voltage level based at least in part on an analog feedback signal received onto the integrated circuit via the second terminal, and in a second mode is for stopping the on pulse by driving the control signal to the second voltage level based at least in part on a digital feedback signal received from the digital processor, wherein the switching power supply includes the means and also includes components external to the integrated circuit; and

driver circuitry, wherein at least some of the driver circuitry is powered by the supply voltage generated by the switching power supply, and wherein the driver circuitry includes at least one driver taken from the group consisting of;

a high-side driver, a low-side driver, and an open-drain driver.

21. The integrated circuit of claim 20, wherein the means includes an error node, wherein in the first mode an analog signal path extends from the second terminal, through an error amplifier, and to the error node, and wherein in the second mode the digital feedback signal is converted into a corresponding analog signal and the corresponding analog signal is supplied onto the error node by clamping a voltage on the error node to a voltage that corresponds to the digital feedback signal.

22. The integrated circuit of claim 20, wherein the means includes a Digital-to-Analog Converter (DAC), and wherein the digital feedback signal is a multi-bit digital signal received by the DAC.

23. The integrated circuit of claim 20, further comprising:

a third terminal; and

linear regulator circuitry that converts a voltage present on the third terminal into a regulated supply voltage, and wherein the regulated supply voltage at least in part powers the means but does not power the digital processor.

24. The integrated circuit of claim 20, wherein the digital processor controls whether the means operates in the first mode or in the second mode.