SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH GUARANTEED TRANSIENT DEADLINES

• US 20130151879A1
• Filed: 02/05/2013
• Published: 06/13/2013
• Est. Priority Date: 12/16/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Thomson, Steven S., Rychlik, Bohuslav, Iranli, Ali, Sur, Sumit, Gargash, Norman S.
• Granted Patent: US 9,176,572 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors.

Claims

1. A method of improving performance on a computing device having multiple processors, the method comprising:

determining a steady state workload of a first processor;

determining an amount of work required to perform the determined steady state workload on the first processor;

computing a performance guarantee value for a processing group that includes the first processor and a second processor;

transitioning the first processor from an idle state to a busy state;

performing dynamic clock and voltage scaling operations to scale a frequency of the first processor based on an actual workload of the first processor;

determining whether the first and second processors have remained in the busy state for a combined period greater than or equal to a sum of the determined amount of work and the performance guarantee value; and

increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value.

2. The method of claim 1, wherein increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value comprises:

increasing the frequency of the first or second processor to a maximum processor frequency.

3. The method of claim 1, wherein increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value comprises increasing the frequency of the first or second processor in steps, the method further comprising repeatedly performing the operations of:

updating the performance guarantee value based on a scaled frequency;

determining whether the first and second processors have remained in the busy state for a combined period greater than or equal to a sum of the determined amount of work and the performance guarantee value; and

increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value.

4. The method of claim 1, wherein computing a performance guarantee value for a processing group that includes the first processor and a second processor comprises computing a deadline value.

5. The method of claim 1, wherein computing a performance guarantee value for a processing group that includes the first processor and a second processor comprises computing a budget value.

6. The method of claim 1, wherein computing a performance guarantee value for a processing group that includes the first processor and a second processor comprises determining requirements of tasks scheduled to execute on the first processor.

7. The method of claim 1, further comprising:

generating pulse trains by sampling transitions between busy and idle states.

8. The method of claim 1, wherein the operations of determining a steady state workload of the first processor, determining an amount of work required to perform steady state workload on the first processor, and computing a performance guarantee value for a processing group that includes the first processor and a second processor are performed by a single thread.

9. The method of claim 8, wherein the single thread executes on the first processor.

10. The method of claim 8, wherein the single thread executes on the second processor of the computing device.

11. A computing device, comprising:

a first processor;

a second processor;

means for determining a steady state workload of the first processor;

means for determining an amount of work required to perform the determined steady state workload on the first processor;

means for computing a performance guarantee value for a processing group that includes the first processor and the second processor;

means for transitioning the first processor from an idle state to a busy state;

means for performing dynamic clock and voltage scaling operations to scale a frequency of the first processor based on an actual workload of the first processor;

means for determining whether the first and second processors have remained in the busy state for a combined period greater than or equal to a sum of the determined amount of work and the performance guarantee value; and

means for increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value.

12. The computing device of claim 11, wherein means for increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value comprises:

means for increasing the frequency of the first or second processor to a maximum processor frequency.

13. The computing device of claim 11, wherein means for increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value comprises means for increasing the frequency of the first or second processor in steps, the computing device further comprising:

means for repeatedly performing the operations of;

updating the performance guarantee value based on a scaled frequency;

determining whether the first and second processors have remained in the busy state for a combined period greater than or equal to a sum of the determined amount of work and the performance guarantee value; and

increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value.

14. The computing device of claim 11, wherein means for computing a performance guarantee value for a processing group that includes the first processor and a second processor comprises means for computing a deadline value.

15. The computing device of claim 11, wherein means for computing a performance guarantee value for a processing group that includes the first processor and a second processor comprises means for computing a budget value.

16. The computing device of claim 11, wherein means for computing a performance guarantee value for a processing group that includes the first processor and a second processor comprises means for determining requirements of tasks scheduled to execute on the first processor.

17. The computing device of claim 11, further comprising:

means for generating pulse trains by sampling transitions between busy and idle states.

18. The computing device of claim 11, further comprising means for accomplishing the operations of determining a steady state workload of the first processor, determining an amount of work required to perform steady state workload, and computing a performance guarantee value via a single thread.

19. The computing device of claim 18, further comprising means for executing single thread on the first processor.

20. The computing device of claim 18, further comprising means for executing the single thread on the second processor of the computing device.

21. A computing device comprising:

a first processor;

a second processor; and

a primary processor configured with processor-executable instructions to perform operations comprising;

determining a steady state workload of the first processor;

determining an amount of work required to perform the determined steady state workload on the first processor;

computing a performance guarantee value for a processing group that includes the first processor and the second processor;

transitioning the first processor from an idle state to a busy state;

performing dynamic clock and voltage scaling operations to scale a frequency of the first processor based on an actual workload of the first processor;

determining whether the first and second processors have remained in the busy state for a combined period greater than or equal to a sum of the determined amount of work and the performance guarantee value; and

increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value.

22. The computing device of claim 21, wherein the primary processor is configured with processor-executable instructions to perform operations such that increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value comprises:

increasing the frequency of the first or second processor to a maximum processor frequency.

23. The computing device of claim 21, wherein:

the primary processor is configured with processor-executable instructions to perform operations such such that increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value comprises increasing the frequency of the first or second processor in steps; and

the primary processor is configured with processor-executable instructions to repeatedly perform the operations of;

updating the performance guarantee value based on a scaled frequency;

determining whether the first and second processors have remained in the busy state for a combined period greater than or equal to a sum of the determined amount of work and the performance guarantee value; and

increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value.

24. The computing device of claim 21, wherein the primary processor is configured with processor-executable instructions to perform operations such such that computing a performance guarantee value for a processing group that includes the first processor and a second processor comprises computing a deadline value.

25. The computing device of claim 21, wherein the primary processor is configured with processor-executable instructions to perform operations such such that computing a performance guarantee value for a processing group that includes the first processor and a second processor comprises computing a budget value.

26. The computing device of claim 21, wherein the primary processor is configured with processor-executable instructions to perform operations such such that computing a performance guarantee value for a processing group that includes the first processor and a second processor comprises determining requirements of tasks scheduled to execute on the first processor.

27. The computing device of claim 21, wherein the primary processor is configured with processor-executable instructions to perform operations such further comprising:

generating pulse trains by sampling transitions between busy and idle states.

28. The computing device of claim 21, wherein the primary processor is configured with processor-executable instructions to perform operations such such that the operations of determining a steady state workload of the first processor, determining an amount of work required to perform steady state workload on the first processor, and computing a performance guarantee value for a processing group that includes the first processor and a second processor are performed by a single thread.

29. The computing device of claim 28, wherein the first processor is the primary processor.

30. The computing device of claim 28, wherein the second processor is the primary processor.

31. A non-transitory computer readable storage medium having stored thereon processor-executable software instructions configured to cause a primary processor to perform operations comprising:

determining a steady state workload of a first processor;

determining an amount of work required to perform the determined steady state workload on the first processor;

computing a performance guarantee value for a processing group that includes the first processor and a second processor;

transitioning the first processor from an idle state to a busy state;

performing dynamic clock and voltage scaling operations to scale a frequency of the first processor based on an actual workload of the first processor;

determining whether the first and second processors have remained in the busy state for a combined period greater than or equal to a sum of the determined amount of work and the performance guarantee value; and

increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value.

32. The non-transitory computer readable storage medium of claim 31, wherein the stored processor-executable software instructions are configured to cause the primary processor to perform operations such that increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value comprises:

increasing the frequency of the first or second processor to a maximum processor frequency.

33. The non-transitory computer readable storage medium of claim 31, wherein:

the stored processor-executable software instructions are configured to cause the primary processor to perform operations such that increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value comprises increasing the frequency of the first or second processor in steps, and

the stored processor-executable software instructions are configured to cause the primary processor to repeatedly perform the operations of;

updating the performance guarantee value based on a scaled frequency;

determining whether the first and second processors have remained in the busy state for a combined period greater than or equal to a sum of the determined amount of work and the performance guarantee value; and

increasing the frequency of one of the first and second processors when it is determined that the first and second processors have remained in the busy state for a combined period that is greater than or equal to a sum of the determined amount of work and the performance guarantee value.

34. The non-transitory computer readable storage medium of claim 31, wherein the stored processor-executable software instructions are configured to cause the primary processor to perform operations such that computing a performance guarantee value for a processing group that includes the first processor and a second processor comprises computing a deadline value.

35. The non-transitory computer readable storage medium of claim 31, wherein the stored processor-executable software instructions are configured to cause the primary processor to perform operations such that computing a performance guarantee value for a processing group that includes the first processor and a second processor comprises computing a budget value.

36. The non-transitory computer readable storage medium of claim 31, wherein the stored processor-executable software instructions are configured to cause the primary processor to perform operations such that computing a performance guarantee value for a processing group that includes the first processor and a second processor comprises determining requirements of tasks scheduled to execute on the first processor.

37. The non-transitory computer readable storage medium of claim 31, the stored processor-executable software instructions are configured to cause the primary processor to perform operations further comprising:

generating pulse trains by sampling transitions between busy and idle states.

38. The non-transitory computer readable storage medium of claim 31, wherein the stored processor-executable software instructions are configured to cause the primary processor to perform operations such that the operations of determining a steady state workload of the first processor, determining an amount of work required to perform steady state workload on the first processor, and computing a performance guarantee value for a processing group that includes the first processor and a second processor are performed by a single thread.

39. The non-transitory computer readable storage medium of claim 38, wherein the stored processor-executable software instructions are configured to cause the primary processor to perform operations the first processor is the primary processor.

40. The non-transitory computer readable storage medium of claim 38, wherein the stored processor-executable software instructions are configured to cause the primary processor to perform operations the second processor is the primary processor.