Programmable Fault Protect for Processor Controlled High-Side and Low-Side Drivers

• US 20130151919A1
• Filed: 04/24/2012
• Published: 06/13/2013
• Est. Priority Date: 12/08/2011
• Status: Active Grant

• Current Assignee: Active-Semi, Inc. (Qorvo, Inc.)
• Original Assignee: Active-Semi, Inc. (Qorvo, Inc.)
• Inventors: Huynh, Steven
• Granted Patent: US 8,892,914 B2
• Time in Patent Office: Days
• US Class Current: 714/746
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: Y02B 20/30 Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Abstract

A Multi-Tile Power Management Integrated Circuit (MTPMIC) includes a processor, a fault protect circuit, a first terminal, a driver that drives the first terminal, a second terminal, and detection circuitry that outputs a digital detection signal indicative of whether a predetermined condition is detected on the second terminal. The processor can program the fault protect circuit so that the fault protect circuit will later disable the driver as a function of multiple signals, including the digital detection signal. The function is programmable by the processor. In one example, if the detection circuitry detects the predetermined condition on the second terminal then the fault protect circuit disables all the high-side drivers and all low-side drivers of the MTPMIC independently of and without input from the processor.

Claims

1. An integrated circuit comprising:

a processor that causes a digital output data signal to be generated;

a first terminal;

a high-side driver coupled to the first terminal, wherein the high-side driver is adapted to drive a control signal on the first terminal high if the digital output data signal has a first value provided that the high-side driver is not disabled, whereas the high-side driver is adapted to drive the control signal on the first terminal low if the digital output data signal has a second value;

a second terminal;

a detection circuit that outputs a digital detection signal indicative of whether a predetermined condition is detected on the second terminal; and

a fault protect circuit that is programmable by the processor to disable the high-side driver as a function of multiple signals received by the fault protect circuit, wherein the digital detection signal from the detection circuit is one of the multiple signals, wherein the function is programmable by the processor, and wherein once programmed then the fault protect circuit can disable the high-side driver without input from the processor even if the digital output data signal has the first value.

2. The integrated circuit of claim 1, wherein the processor causes the digital output data signal to be generated by writing data onto a bus, wherein the data is communicated via the bus to a driver manager tile, and wherein the high-side driver is a part of the driver manager tile.

3. The integrated circuit of claim 1, further comprising:

a bootstrap terminal, wherein the high-side driver drives the control signal high by coupling the first terminal to the bootstrap terminal; and

a floating source terminal, wherein the high-side driver drives the control signal low by coupling the first terminal to the floating source terminal.

4. The integrated circuit of claim 1, wherein the predetermined condition is a condition in which a voltage on the second terminal is above a predetermined voltage, and wherein the predetermined voltage is programmable by the processor.

5. The integrated circuit of claim 1, further comprising:

a third terminal, wherein the detection circuit comprises a differential amplifier that amplifies a voltage difference between a voltage on the second terminal and a voltage on the third terminal.

6. The integrated circuit of claim 1, wherein the detection circuit comprises:

a differential amplifier that can receive a voltage from the second terminal;

a sample/hold circuit that receives a signal output by the differential amplifier;

a detection threshold voltage generating circuit that outputs a detection threshold voltage; and

a comparator having a first input lead, a second input lead, and an output lead, wherein the comparator receives a signal output by the sample/hold circuit onto the first input lead of the comparator, wherein the comparator receives the detection threshold voltage onto the second input lead of the comparator, and wherein the comparator outputs the digital detection signal onto the output lead of the comparator.

7. The integrated circuit of claim 1, wherein the function is determined by information stored in a plurality of programmable bits, wherein the processor can change the information and thereby can change the function.

8. An integrated circuit comprising:

a first terminal;

a detection threshold voltage generating circuit that outputs a detection threshold voltage;

a first comparator that outputs a first detection signal indicative of whether a voltage on the first terminal has a predetermined relationship with respect to the detection threshold voltage;

a second terminal;

a first driver coupled to drive a control signal onto the second terminal;

a plurality of programmable bits that can store first digital information or second digital information;

a fault protect circuit coupled to the programmable bits, wherein if the programmable bits store the first digital information then the first driver is disabled if the first detection signal indicates that the voltage on the first terminal has the predetermined relationship with respect to the detection threshold voltage;

a memory; and

a processor adapted to access the memory and to execute instructions stored in the memory, wherein the processor is configured so that it can write a selectable one of either the first digital information or the second digital information into the plurality of programmable bits.

9. The integrated circuit of claim 8, wherein a signal path extends from the first terminal, through the first comparator, through the fault protect circuit, and to the first driver, wherein a signal propagating through the signal path causes the first driver to be disabled, and wherein the signal path does not pass through the processor.

10. The integrated circuit of claim 9, further comprising:

a bootstrap terminal, wherein the first driver is a high-side driver coupled to the bootstrap terminal.

11. The integrated circuit of claim 9, wherein the first terminal is coupled to a current sense resistor external to the integrated circuit.

12. The integrated circuit of claim 9, further comprising:

a third terminal; and

a second driver coupled to drive a control signal onto the third terminal, wherein the first driver is a high-side driver coupled to drive a high-side transistor external to the integrated circuit, and wherein the second driver is a low-side driver coupled to drive a low-side transistor external to the integrated circuit.

13. The integrated circuit of claim 9, wherein the detection threshold voltage is programmable and can be changed by the processor.

14. The integrated circuit of claim 9, further comprising:

a third terminal;

a second driver coupled to drive a control signal onto the third terminal, and

wherein the fault protect circuit comprises an anti-shoot through circuit that prevents the first driver from asserting the control signal onto the second terminal if the second driver is asserting a control signal onto the third terminal, and wherein the anti-shoot through circuit prevents the second driver from asserting the control signal onto the third terminal if the first driver is asserting the control signal onto the second terminal.

15. The integrated circuit of claim 9, further comprising:

a third terminal, wherein the voltage on the first terminal is a voltage relative to a voltage on the third terminal; and

a differential amplifier coupled to amplify the voltage on the first terminal relative to the voltage on the third terminal, wherein the differential amplifier supplies an output signal to the first comparator.

16. The integrated circuit of claim 15, wherein the differential amplifier has a gain, and wherein the processor can change the gain of the differential amplifier.

17. The integrated circuit of claim 9, further comprising:

a third terminal; and

a second comparator that outputs a second detection signal indicative of whether a voltage on the third terminal has a predetermined relationship with respect to the detection threshold voltage.

18. The integrated circuit of claim 8, further comprising:

a third terminal; and

a second comparator that outputs a second detection signal indicative of whether a voltage on the third terminal has a predetermined relationship with respect to the detection threshold voltage, wherein the fault protect circuit receives the first detection signal and the second detection signal, wherein the fault protect circuit is programmable by the processor so that the first driver is disabled in accordance with a predetermined combinatorial logic function of the first and second detection signals, and wherein the processor can change the predetermined combinatorial logic function.

19. The integrated circuit of claim 8, further comprising:

a third terminal; and

a second comparator that outputs a second detection signal indicative of whether a voltage on the third terminal has a predetermined relationship with respect to the detection threshold voltage, wherein the fault protect circuit receives the first detection signal and the second detection signal and disables the first driver if a predetermined one of the first and second detection signals has a predetermined digital value.

20. The integrated circuit of claim 8, further comprising:

a third terminal;

a second driver coupled to drive a control signal onto the third terminal, wherein the fault protect circuit is programmable by the processor to disable one of the first and second drivers, wherein which one of the first and second driver is disabled by the fault protect circuit is based at least in part on the first detection signal.

21. A method comprising:

generating a digital output data signal using a processor, wherein a high-side driver is adapted to drive a control signal on a first terminal to a first logic state if the digital output data signal has a first value provided that the high-side driver is not disabled, whereas the high-side driver is adapted to drive the control signal on the first terminal to a second logic state if the digital output data signal has a second value;

detecting a predetermined condition on the second terminal and in response asserting a digital detection signal; and

disabling the high-side driver as a function of multiple signals received by a fault protect circuit, wherein the digital detection signal from the detection circuit is one of the multiple signals, wherein the function is programmable by the processor, wherein once programmed then the fault protect circuit can disable the high-side driver without input from the processor even if the digital output data signal supplied by the processor has the first value, and wherein the processor, the high-side driver, the first terminal, the second terminal, and the fault protect circuit are all parts of an integrated circuit.

22. The method of claim 21, wherein the detection circuit comprises a differential amplifier that amplifies a voltage difference between a voltage on the second terminal and a voltage on a third terminal of the integrated circuit, and wherein the steps of generating the digital output data signak, of detecting a predetermined condition, and of disabling the high-side driver are performed by the integrated circuit.

23. The method of claim 21, wherein the processor writes data onto a bus and thereby causes the digital output data signal to be generated, wherein the first logic state involves coupling the first terminal to a bootstrap terminal through the high-side driver, and wherein the second logic state involves coupling the first terminal to a floating terminal through the high-side driver.