DISTRIBUTING SPARE LATCH CIRCUITS IN INTEGRATED CIRCUIT DESIGNS

• US 20130152029A1
• Filed: 12/09/2011
• Published: 06/13/2013
• Est. Priority Date: 12/09/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: AGRAWAL, Mitesh A., BALASUBRAMANIAN, Santosh, CHATNAHALLI, Pradeep N., SHIVARAM, Prasad
• Granted Patent: US 8,490,039 B2
• Time in Patent Office: Days
• US Class Current: 716/104
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

Methods for allocating spare latch circuits to logic blocks in an integrated circuit design are provided. A method includes determining logic blocks in the design and determining and determining an allocation of spare latch circuits among the logic blocks based on respective attributes of the logic blocks. The method further include placing the spare latch circuits in the design in accordance with the determined allocation based on local clock buffers corresponding with the logic blocks.

Claims

1. A method for allocating spare latches in a design, comprising:

determining logic blocks in an integrated circuit (IC) design;

determining an allocation of spare latch circuits among the logic blocks based on respective attributes of the logic blocks; and

placing the spare latch circuits in the IC design in accordance with the determined allocation based on local clock buffers corresponding to the logic blocks in the IC design,

wherein the determining, the allocation, and the placing are performed using a computer device.

2. The method of claim 1, wherein the placing the spare latch circuits in the IC design in accordance with the determined allocation comprises dividing a number of the spare latch circuits allocated to each of the logic blocks equally among respective local clock buffers of the logic blocks.

3. The method of claim 1, wherein the attributes of the logic blocks include at least one of:

an age of a logic block design, a number of times the logic block design has previously been used in an IC, a number of bugs that have been found in the logic block design, a complexity of the logic block design, and a percentage of the logic block design that has been verified.

4. The method of claim 3, further comprising obtaining one or more of the attributes from hardware definition language (HDL) information corresponding to the logic block design.

5. The method of claim 3, further comprising receiving one or more of the attributes from a user via an interactive user interface.

6. The method of claim 3, further comprising retrieving one or more of the attributes from a logic block verification database.

7. The method of claim 1, wherein the determining the allocation comprises, for each of the logic blocks, determining a likelihood that a logic block design will change based on the respective attributes of the logic block.

8. The method of claim 7, wherein the determining the likelihood that the logic block design will change comprises:

determining a weighted average of the attributes for each of the logic blocks; and

normalizing each of the weighted averages across the logic blocks.

9. The method of claim 1, wherein the spare latch circuits include a latch, a buffer and a clocking structure.

10. The method of claim 1, wherein the number of spare latch circuits in the IC design is a predetermined value.

21. The method of claim 1, wherein the determining the allocation of spare latch circuits comprises:

obtaining, for each of the logic blocks, one or more of the attributes representing a likelihood of a design change relative to other logic blocks in the design; and

determining for each of the logic blocks a likelihood that a design change will be made to the logic blocks based on the one or more attributes of the logic blocks.

11-20. -20. (canceled)

22. A method for allocating spare latches in a design, comprising:

determining logic blocks in an integrated circuit (IC) design;

determining for each of the logic blocks a likelihood of design change based on the respective attributes of the logic block;

determining an allocation of spare latch circuits among the logic blocks based on the respective likelihood of design change of the logic blocks; and

placing the spare latch circuits in the IC design in accordance with the determined allocation,

wherein the determining the logic blocks, the determining the likelihood, the determining the allocation, and the placing are performed using a computer device.

23. The method of claim 22, wherein the placing the spare latch circuits in the IC design in accordance with the determined allocation comprises dividing a number of the spare latch circuits allocated to each of the logic blocks equally among respective local clock buffers of the logic blocks.

24. The method of claim 22, wherein the attributes of the logic blocks include at least one of:

an age of a logic block design, a number of times the logic block design has previously been used in an IC, a number of bugs that have been found in the logic block design, a complexity of the logic block design, and a percentage of the logic block design that has been verified.

25. The method of claim 22, wherein the determining the likelihood of design change comprises:

determining a weighted average of the attributes for each of the logic blocks; and

normalizing each of the weighted averages across the logic blocks.