METHOD AND APPARATUS FOR MANAGING THE CONFIGURATION AND FUNCTIONALITY OF A SEMICONDUCTOR DESIGN

• US 20130152031A1
• Filed: 01/30/2013
• Published: 06/13/2013
• Est. Priority Date: 10/14/1998
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Khan, Mohammed Noshad, Plowman, Edward, Hakewill, James Robert-Howard
• Granted Patent: US 9,171,114 B2
• Time in Patent Office: Days
• US Class Current: 716/104
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields

Abstract

A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Claims

1. A computer-implemented method of generating at least a portion of an integrated circuit design, the method comprising:

providing a user with an integrated circuit design for a processor or processor peripheral device, the integrated circuit design described by a hardware description language model;

assigning default values to a plurality of design parameters from a set of design parameters for the hardware description language model, the plurality of design parameters including a clock parameter, a memory parameter, or a cache parameter;

receiving one or more inputs from the user for at least one of the set of design parameters to customize the integrated circuit design responsive to assigning the default values, the inputted design parameter including at least one of a processor cache size, a processor cache length, a size of external memory space to be cached, a clock period, or a clock skew; and

generating an updated hardware description language model for the integrated circuit design based on the set of design parameters updated based on the one or more inputs and the hardware description language model.

2. The method of claim 1, further comprising:

verifying an integrated circuit synthesized from the updated hardware description language model.

3. The method of claim 2, wherein the integrated circuit is synthesized on a field programmable gate array.

4. The method of claim 1, wherein the inputted design parameter further includes at least one of an overall device or system configuration, width of an external memory system data bus, cache type, or cache size.

5. The method of claim 1, wherein the processor or processor peripheral device comprises a reduced instruction set computing (RISC) processor, and the hardware description language model comprises a VHDL model.

6. The method of claim 1, further comprising:

causing a first computer program to write a second computer program, the second program configured to perform a specific task based at least in part on the one or more inputs from the user; and

executing the second program to perform the specific task.

7. The method of claim 6, wherein the specific task comprises one selected from the group consisting of generating a simulation makefile for a simulation of the integrated circuit design, generating a synthesis makefile for a synthesis of the integrated circuit design.

8. The method of claim 1, further comprising:

evaluating an acceptability of the updated hardware description language model using test code.

9. The method of claim 1, further comprising:

testing the updated hardware description language through simulation or synthesis using test code to generate an output;

receiving one or more additional inputs from the user responsive to determining that the output does not meet performance criteria; and

generating a second customized hardware description language model based on the additional inputs.

10. The method of claim 1, wherein automatically generating the updated hardware description language model comprises:

receiving an identification of a location of one or more library files that provide at least one prototype description for the integrated circuit design; and

generating the updated hardware description language model based at least in part on the at least one prototype description.

11. The method of claim 10, wherein generating the updated hardware description language model comprises:

modifying the at least one prototype description to include substituted values for values included in the at least one prototype description based at least in part on the at least one received design parameter.

12. The method of claim 1, wherein the one or more inputs are received from the user through a graphical user interface.

13. The method of claim 1, wherein the one or more inputs are received from the user in a non-description language format.

14. A computer program product for generating at least a portion of an integrated circuit design, the computer program product comprising a non-transitory computer-readable storage medium storing executable instructions, the instructions when executed by a first processor are configured to:

provide a user with an integrated circuit design for a second processor or processor peripheral device, the integrated circuit design described by a hardware description language model;

assign default values to a plurality of design parameters from a set of design parameters for the hardware description language model, the plurality of design parameters including a clock parameter, a memory parameter, or a cache parameter;

receive one or more inputs from the user for at least one of the set of design parameters to customize the integrated circuit design responsive to assigning the default values, the inputted design parameter including at least one of a processor cache size, a processor cache length, a size of external memory space to be cached, a clock period, or a clock skew; and

generate an updated hardware description language model for the integrated circuit design based on the set of design parameters updated based on the one or more inputs and the hardware description language model.

15. The computer program product of claim 14, the instructions when executed by the first processor are further configured to:

verify an integrated circuit synthesized from the updated hardware description language model.

16. The computer program product of claim 14, wherein the inputted design parameter further includes at least one of an overall device or system configuration, width of an external memory system data bus, cache type, or cache size.

17. The computer program product of claim 14, wherein the second processor or processor peripheral device comprises a reduced instruction set computing (RISC) processor, and the hardware description language model comprises a VHDL model.

18. The computer program product of claim 14, the instructions when executed by the first processor are further configured to:

test the updated hardware description language through simulation or synthesis using test code to generate an output;

receive one or more additional inputs from the user responsive to determining that the output does not meet performance criteria; and

generate a second customized hardware description language model based on the additional inputs.

19. The computer program product of claim 14, wherein generating the updated hardware description language model comprises:

receiving an identification of a location of one or more library files that provide at least one prototype description for the integrated circuit design; and

generating the updated hardware description language model based at least in part on the at least one prototype description.

20. A computer system for generating at least a portion of an integrated circuit design, the computer system comprising:

a computer processor; and

a computer-readable storage medium storing executable instructions, the instructions when executed by the computer processor are configured to;

provide a user with an integrated circuit design for a processor or processor peripheral device, the integrated circuit design described by a hardware description language model;

assign default values to a plurality of design parameters from a set of design parameters for the hardware description language model, the plurality of design parameters including a clock parameter, a memory parameter, or a cache parameter;

receive one or more inputs from the user for at least one of the set of design parameters to customize the integrated circuit design responsive to assigning the default values, the inputted design parameter including at least one of a processor cache size, a processor cache length, a size of external memory space to be cached, a clock period, or a clock skew; and

generate an updated hardware description language model for the integrated circuit design based on the set of design parameters updated based on the one or more inputs and the hardware description language model.