ELECTRICALLY BONDED ARRAYS OF TRANSFER PRINTED ACTIVE COMPONENTS

• US 20130153277A1
• Filed: 03/22/2011
• Published: 06/20/2013
• Est. Priority Date: 03/29/2010
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: Philip Garrou
• Inventors: Bower, Christopher, Meitl, Matthew, Garrou, Philip, Menard, Etienne
• Granted Patent: US 9,049,797 B2
• Time in Patent Office: Days
• US Class Current: 174/260
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/08238 the bonding area connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24147 the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/245 Material
• CPC Class Codes: H01L 2224/24998 Reinforcing structures, e.g. ramp-like support
• CPC Class Codes: H01L 2224/2731 in liquid form
• CPC Class Codes: H01L 2224/29078 : being disposed next to each other, e.g. side-to-side arrangements
• CPC Class Codes: H01L 2224/291 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/29101 : the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/2929 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29344 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/3012 : Layout
• CPC Class Codes: H01L 2224/32104 : relative to the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32146 : the layer connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/32227 : the layer connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/76155 : Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/80203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/80224 : using a laser
• CPC Class Codes: H01L 2224/81192 : wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/82007 : involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
• CPC Class Codes: H01L 2224/821 : Forming a build-up interconnect
• CPC Class Codes: H01L 2224/82102 : using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/82106 : by subtractive methods
• CPC Class Codes: H01L 2224/83093 : Transient conditions, e.g. gas-flow
• CPC Class Codes: H01L 2224/83121 : Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/83815 : Reflow soldering
• CPC Class Codes: H01L 2224/8384 : Sintering
• CPC Class Codes: H01L 2224/83851 : being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/83855 : Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/83859 : Localised curing of parts of the layer connector
• CPC Class Codes: H01L 2224/83862 : Heat curing
• CPC Class Codes: H01L 2224/83868 : Infrared [IR] curing
• CPC Class Codes: H01L 2224/83871 : Visible light curing
• CPC Class Codes: H01L 2224/83874 : Ultraviolet [UV] curing
• CPC Class Codes: H01L 2224/92143 : the second connecting process involving a bump connector
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/30 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 27/1214 : comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 : the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01S 5/02315 : Support members, e.g. bases or carriers
• CPC Class Codes: H01S 5/0233 : Mounting configuration of laser chips
• CPC Class Codes: H01S 5/02345 : Wire-bonding
• CPC Class Codes: H01S 5/0235 : Method for mounting laser chips
• CPC Class Codes: H05K 1/18 : Printed circuits structurally associated with non-printed electric components H05K1/0201, H05K1/023, H05K1/0243, and H05K1/16 take precedence
• CPC Class Codes: H05K 3/0058 : Laminating printed circuit boards onto other substrates, e.g. metallic substrates H05K1/0281 takes precedence
• CPC Class Codes: H05K 3/10 : in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49139 : by inserting component lead or terminal into base aperture

Abstract

An active component array includes a target substrate having one or more contacts formed on a side of the target substrate, and one or more printable active components distributed over the target substrate. Each active component includes an active layer having a top side and an opposing bottom side and one or more active element(s) formed on or in the top side of the active layer. The active element(s) are electrically connected to the contact(s), and the bottom side is adhered to the target substrate. Related fabrication methods are also discussed.

Claims

1. An active component array, comprising:

at least one printable electronic component comprising an active layer including at least one active element on a first surface thereof and a conductive element on a second surface thereof opposite the first surface, the conductive element on the second surface being configured to provide an electrical coupling to the at least one active element on the first surface, wherein the at least one electronic component includes a broken portion of a tether adjacent a periphery thereof; and

a target substrate different from the active layer and including one or more electrical contacts on a surface thereof, wherein the at least one electronic component is printed on the target substrate such that the conductive element on the second surface thereof is in contact with a respective one of the electrical contacts on the surface of the substrate.

2. The array of claim 1, wherein the tether is configured to releasably adhere the at least one electronic component to an anchor portion of the active layer on a source substrate.

3. The array of claim 2, wherein the at least one electronic component comprises a plurality of electronic components printed on the target substrate, and wherein, in each of the electronic components, the first surface is configured to be adhered to a stamp to transfer the respective electronic component from the source substrate to the target substrate.

4. The array of claim 1, further comprising:

an adhesive layer between the second surface of the at least one electronic component and the surface of the target substrate.

5. The array of claim 4, wherein the adhesive layer comprises a conductive layer between the conductive element of the at least one electronic component and the respective one of the electrical contacts.

6. The array of claim 5, wherein the adhesive layer comprises a material configured to transition between a nonconductive state and a conductive state responsive to curing thereof.

7. The array of claim 5, wherein the adhesive layer comprises a eutectic layer, a conductive film, and/or conductive nano-particles.

8. The array of claim 1, wherein the at least one electronic component includes a via extending therethrough from the first surface to the second surface, and wherein the conductive element extends through the via from the at least one active component on the first surface to the second surface.

9. The array of claim 8, wherein the conductive element protrudes from the second surface.

10. The array of claim 1, wherein the conductive element extends from the at least one active component on the first surface to the second surface around a periphery of the active layer.

11. The array of claim 1, wherein the conductive element is a diode comprising a first doped layer and a second doped layer having a conductivity type opposite that of the first doped layer.

12. The array of claim 1, wherein the target substrate includes conductive traces thereon, and wherein ones of the conductive traces are coupled to ones of the electrical contacts.

13. The array of claim 1, wherein the target substrate comprises a a flexible and/or a polymer substrate.

14. The array of claim 12, wherein the active layer comprises a crystalline, microcrystalline, polycrystalline, or amorphous semiconductor layer.

15. The array of claim 1, wherein the target substrate including the at least one electronic component printed thereon defines a surface mount package for a chip-level device.

16. A method of fabricating an active component array, the method comprising:

providing at least one printable electronic component comprising an active layer including at least one active element on a first surface thereof and a conductive element on a second surface thereof opposite the first surface, the conductive element on the second surface being configured to provide an electrical coupling to the at least one active element on the first surface, wherein the at least one electronic component includes a broken portion of a tether adjacent a periphery thereof; and

printing the at least one electronic component on a target substrate different from the active layer and including one or more electrical contacts on a surface thereof such that the conductive element on the second surface of the at least one electronic component is in contact with a respective one of the electrical contacts.

17. The method of claim 16, wherein the tether is configured to releasably adhere the at least one electronic component to an anchor portion of the active layer on a source substrate.

18. The method of claim 17, wherein the at least one electronic component comprises a plurality of electronic components, and wherein printing comprises:

providing the plurality of electronic components releasably adhered to the source substrate by respective tethers;

pressing a stamp on the source substrate to break the respective tethers and adhere the first surface of each of the electronic components to the stamp;

aligning the stamp including the plurality of electronic components thereon with the electrical contacts on the surface of the target substrate;

pressing the stamp on the target substrate such that the conductive element on the second surface of each of the electronic components contacts a respective one of the electrical contacts on the surface of the target substrate; and

separating the stamp from the target substrate to print the plurality of electrical components thereon.

19. The method of claim 18, wherein providing the plurality of electronic components comprises:

providing the source substrate including a sacrificial layer thereon and the active layer on the sacrificial layer;

processing the active layer to define the plurality of electronic components respectively including the at least one active element on the first surface thereof, respective trenches extending around each of the electronic components, and the respective tethers connecting each of the electronic components to respective anchor portions of the active layer; and

removing portions of the sacrificial layer between the plurality of electronic components and the source substrate such that the plurality of electronic components are releasably adhered to the source substrate by the respective tethers.

20. The method of claim 18, wherein pressing the stamp on the target substrate is preceded by:

providing an adhesive layer between the second surface of each of the electronic components and the surface of the target substrate.

21. The method of claim 20, wherein the adhesive layer comprises a conductive layer provided between the conductive element of each of the electronic components and the respective one of the electrical contacts on the target substrate.

22. The method of claim 21, wherein separating the stamp from the target substrate is preceded by:

curing the adhesive layer to adhere the plurality of electronic components to the target substrate,

wherein an adhesive strength of the adhesive layer is greater than that used to adhere the first surface of each of the electronic components to the stamp.

23. The method of claim 22, wherein the adhesive layer comprises a material configured to transition between a nonconductive state and a conductive state responsive to the curing thereof.

24. The method of claim 23, wherein curing comprises selectively irradiating portions of the adhesive layer through the target substrate, the stamp, and/or the electronic components using light, heat, and/or electromagnetic energy.

25. The method of claim 22, wherein the adhesive layer comprises a eutectic layer, an anisotropic conductive film, and/or conductive nano-particles.

26. The method of claim 25, wherein the conductive nano-particles are provided in a colloid, and further comprising:

depositing the colloid on the surface of the target substrate using an inkjet dispenser or micro-dispenser to define the adhesive layer.

27. The method of claim 18, wherein each of the electrical contacts includes a eutectic layer, and further comprising:

reflowing the eutectic layer such that the conductive element on the second surface of each of the electronic components is in contact with the respective one of the electrical contacts

28. The method of claim 16, wherein the at least one electronic component includes a via extending therethrough from the first surface to the second surface, and wherein the conductive element extends through the via from the at least one active component on the first surface to the second surface.

29. The method of claim 16, wherein the conductive element extends from the at least one active component on the first surface to the second surface around a periphery of the active layer.

30. The method of claim 16, wherein the conductive element is a diode comprising a first doped layer and a second doped layer having a conductivity type opposite that of the first doped layer.

31. The method of claim 16, wherein the target substrate comprises a

a flexible and/or a polymer substrate, and wherein the active layer comprises a crystalline, microcrystalline, polycrystalline, or amorphous semiconductor layer.

32. The method of claim 16, wherein the at least one electronic component comprises at least one active-matrix pixel controller, light-emitting diode, photo-diode, edge laser, or photovoltaic element.