THIN FILM TRANSISTOR ARRAY PANEL HAVING IMPROVED STORAGE CAPACITANCE AND MANUFACTURING METHOD THEREOF

• US 20130153906A1
• Filed: 11/02/2012
• Published: 06/20/2013
• Est. Priority Date: 02/25/2005
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: RYU, Hye-Young, KIM, Sang-Gab, KIM, Jang-Soo, CHIN, Hong-Kee, OH, Min-Seok, CHOE, Hee-Hwan, KIM, Shi-Yul
• Application Number:
  US13/668,082
• Publication Number:
  US 20130153906A1
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136222 Colour filters incorporated in the active matrix substrate
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 2202/02 organic material

Abstract

A thin film transistor array panel is provided, which includes a gate line, a data line intersecting the gate line, a storage electrode apart from the gate and data lines, a thin film transistor connected to the gate and data lines and having a drain electrode, a pixel electrode connected to the drain electrode, a first insulating layer over the thin film transistor and disposed under the pixel electrode, and a second insulating layer disposed on the first insulating layer and having an opening exposing the first insulating layer on the storage electrode.

Claims

1. A thin film transistor array panel, comprising:

a gate line;

a data line intersecting the gate line;

a semiconductor disposed under the data line;

a thin film transistor connected to the gate line and the data line and having a drain electrode;

a first insulating layer disposed on the data line and comprising an organic material;

a pixel electrode disposed on the first insulating layer and connected to the drain electrode;

a shielding electrode disposed in the same layer as the pixel electrode and transmitting a common voltage, the shielding electrode comprising a first portion extending along the data line and covering the data line.

2. The thin film transistor array panel of claim 1, wherein the shielding electrode completely covers boundary edges of the data line.

3. The thin film transistor array panel of claim 2, wherein the shielding electrode overlaps at least a portion of the gate line.

4. The thin film transistor array panel of claim 3, wherein the shielding electrode comprises a second portion extending along the gate line.

5. The thin film transistor array panel of claim 4, wherein a width of the shielding electrode is greater than a width of the data line.

6. The thin film transistor array panel of claim 5, wherein the width of the shielding electrode is less than a width of the gate line.

7. The thin film transistor array panel of claim 4, wherein the width of the shielding electrode is less than a width of the gate line.

8. The thin film transistor array panel of claim 3, wherein a width of the shielding electrode is greater than a width of the data line.

9. The thin film transistor array panel of claim 8, wherein the width of the shielding electrode is less than a width of the gate line.

10. The thin film transistor array panel of claim 3, wherein the width of the shielding electrode is less than a width of the gate line.

11. The thin film transistor array panel of claim 2, wherein the shielding electrode comprises a second portion extending along the gate line.

12. The thin film transistor array panel of claim 11, wherein a width of the shielding electrode is greater than a width of the data line.

13. The thin film transistor array panel of claim 12, wherein the width of the shielding electrode is less than a width of the gate line.

14. The thin film transistor array panel of claim 11, wherein the width of the shielding electrode is less than a width of the gate line.

15. The thin film transistor array panel of claim 2, wherein a width of the shielding electrode is greater than a width of the data line.

16. The thin film transistor array panel of claim 15, wherein the width of the shielding electrode is less than a width of the gate line.

17. The thin film transistor array panel of claim 2, wherein the width of the shielding electrode is less than a width of the gate line.

18. The thin film transistor array panel of claim 1, wherein the shielding electrode overlaps at least a portion of the gate line.

19. The thin film transistor array panel of claim 18, wherein the shielding electrode comprises a second portion extending along the gate line.

20. The thin film transistor array panel of claim 19, wherein a width of the shielding electrode is greater than a width of the data line.

21. The thin film transistor array panel of claim 20, wherein the width of the shielding electrode is less than a width of the gate line.

22. The thin film transistor array panel of claim 19, wherein the width of the shielding electrode is less than a width of the gate line.

23. The thin film transistor array panel of claim 18, wherein a width of the shielding electrode is greater than a width of the data line.

24. The thin film transistor array panel of claim 23, wherein the width of the shielding electrode is less than a width of the gate line.

25. The thin film transistor array panel of claim 18, wherein the width of the shielding electrode is less than a width of the gate line.

26. The thin film transistor array panel of claim 1, wherein the shielding electrode comprises a second portion extending along the gate line.

27. The thin film transistor array panel of claim 26, wherein a width of the shielding electrode is greater than a width of the data line.

28. The thin film transistor array panel of claim 27, wherein the width of the shielding electrode is less than a width of the gate line.

29. The thin film transistor array panel of claim 26, wherein the width of the shielding electrode is less than a width of the gate line.

30. The thin film transistor array panel of claim 1, wherein a width of the shielding electrode is greater than a width of the data line.

31. The thin film transistor array panel of claim 30, wherein the width of the shielding electrode is less than a width of the gate line.

32. The thin film transistor array panel of claim 1, wherein the width of the shielding electrode is less than a width of the gate line.