Integrated Circuits with Components on Both Sides of a Selected Substrate and Methods of Fabrication

• US 20130154088A1
• Filed: 06/20/2012
• Published: 06/20/2013
• Est. Priority Date: 06/22/2011
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Cable, James S., Miscione, Anthony Mark, Reedy, Ronald Eugene
• Granted Patent: US 9,947,688 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 27/0694 comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias

Abstract

Novel integrated circuits (SOI ICs), and methods for making and mounting the ICs are disclosed. In one embodiment, an IC comprises a first circuit layer of the IC formed from an active layer of an SOI wafer. The first circuit layer is coupled to a first surface of buffer layer, and a second surface of the buffer layer is coupled to a selected substrate comprising an insulating material. The selected substrate may be selected, without limitation, from the following types: sapphire, quartz, silicon dioxide glass, piezoelectric materials, and ceramics. A second circuit layer of the IC are formed, coupled to a second surface of the selected substrate. In one embodiment of a mounted IC, the first circuit layer is coupled to contact pads on a package substrate via solder bumps or copper pillars. The second circuit layer is coupled to contact pads on the package substrate via wire bonds.

Claims

1. A method for forming integrated circuits (ICs) comprising a first circuit layer and a second circuit layer, comprising:

a) forming the first circuit layer from an active layer of a silicon-on-insulator (SOI) wafer, wherein the SOI wafer comprises the active layer, a buffer layer coupled to the active layer, and a silicon substrate coupled to the buffer layer;

b) removing the silicon substrate from the buffer layer;

c) coupling the buffer layer to a first surface of a selected substrate; and

,

d) forming the second circuit layer on a second surface of the selected substrate.

2. The method of claim 1, wherein the selected substrate comprises a material selected from the following types of materials:

sapphire, quartz, silicon dioxide glass, aluminum nitride, hot-pressed silicon carbide, sintered silicon carbide, CVD silicon carbide, and alumina.

3. The method of claim 1, wherein the selected substrate comprises sapphire, and wherein the second circuit layer comprises passive components.

4. The method of claim 1, wherein the selected substrate comprises a piezoelectric material, and wherein the second circuit layer comprises acoustic wave components.

5. The method of claim 1, further comprising a thinning the selected substrate, wherein the thinning the selected substrate is performed subsequent to the coupling the buffer layer to a first surface of a selected substrate, and prior to the forming the second circuit layer on a second surface of the selected substrate.

6. The method of claim 1, further comprising:

a) forming contact elements coupled to the first circuit layer; and

,

b) separating the ICs into dies, each die comprising an IC.

7. A method for forming integrated circuits (ICs) comprising a first circuit layer and a second circuit layer, comprising:

a) forming the first circuit layer from an active layer of a silicon-on-insulator (SOI) wafer, wherein the SOI wafer comprises the active layer, a buffer layer coupled to the active layer, and a silicon substrate coupled to the buffer layer;

b) removing the silicon substrate from the buffer layer;

c) forming the second circuit layer on a second surface of the selected substrate; and

,

d) coupling the buffer layer to a first surface of a selected substrate.

8. The method of claim 7, wherein the selected substrate comprises a material selected from the following types of materials:

sapphire, quartz, silicon dioxide glass, aluminum nitride, hot-pressed silicon carbide ceramic, sintered silicon carbide ceramic, CVD silicon carbide, and alumina.

9. The method of claim 7, wherein the selected substrate comprises sapphire, and wherein the second circuit layer comprises passive components.

10. The method of claim 7, wherein the selected substrate comprises a piezoelectric material, and wherein the second circuit layer comprises acoustic wave components.

11. The method of claim 7, further comprising a thinning the selected substrate, wherein the thinning the selected substrate is performed subsequent to the forming the second circuit layer on a second surface of the selected substrate, and prior to the coupling the buffer layer to a first surface of a selected substrate.

12. The method of claim 7, further comprising:

a) forming contact elements coupled to the first circuit layer; and

,

b) separating the ICs into dies, each die comprising an IC.

13. A method for forming integrated circuits (ICs) comprising a first circuit layer and a second circuit layer, comprising:

a) forming the first circuit layer from an active layer of a silicon-on-insulator (SOI) wafer, wherein the SOI wafer comprises the active layer, a buffer layer coupled to the active layer, and a silicon substrate coupled to the buffer layer;

b) removing the silicon substrate from the buffer layer;

c) forming the second circuit layer on a second substrate;

d) separating the second circuit layer from the second substrate;

e) coupling the buffer layer to a first surface of a selected substrate; and

,

f) coupling the second circuit layer to a second surface of the selected substrate.

14. The method of claim 13, wherein the selected substrate comprises a material selected from the following types of materials:

sapphire, quartz, silicon dioxide glass, aluminum nitride, hot-pressed silicon carbide ceramic, sintered silicon carbide ceramic, CVD silicon carbide, and alumina.

15. The method of claim 13, wherein the second substrate is selected from the following:

an SOI substrate, a silicon substrate having an insulating top layer, and a piezoelectric substrate.

16. The method of claim 15, wherein the insulating top layer comprises silicon dioxide.

17. The method of claim 13, wherein the second circuit layer comprises at least one of the following types of components:

active components, passive components, opto-electronic components, microelectromechanical components, and acoustic wave components.

18. The method of claim 13, further comprising a thinning the selected substrate, wherein the thinning the selected substrate is performed subsequent to the coupling the buffer layer to a first surface of a selected substrate, and prior to the coupling the second circuit layer to a second surface of the selected substrate.

19. The method of claim 13, further comprising:

a) forming contact elements coupled to the first circuit layer; and

,

b) separating the ICs into dies, each die comprising an IC.

20. A method for forming integrated circuits (ICs) comprising a first circuit layer and a second circuit layer, comprising:

a) forming the first circuit layer from an active layer of a silicon-on-insulator (SOI) wafer, wherein the SOI wafer comprises the active layer, a buffer layer coupled to the active layer, and a silicon substrate coupled to the buffer layer;

b) removing the silicon substrate from the buffer layer;

c) forming the second circuit layer on a second substrate;

d) separating the second circuit layer from the second substrate;

e) coupling the second circuit layer to a second surface of the selected substrate; and

,

f) coupling the buffer layer to a first surface of a selected substrate.

21. The method of claim 20, wherein the selected substrate comprises a material selected from the following types of materials:

sapphire, quartz, silicon dioxide glass, aluminum nitride, hot-pressed silicon carbide ceramic, sintered silicon carbide ceramic, CVD silicon carbide, and alumina.

22. The method of claim 20, wherein the second substrate is selected from the following:

an SOI substrate, a silicon substrate having an insulating top layer, and a piezoelectric substrate.

23. The method of claim 22, wherein the insulating top layer comprises silicon dioxide.

24. The method of claim 20, wherein the second circuit layer comprises at least one of the following types of components:

active components, passive components, electro-optic components, microelectromechanical components, and acoustic wave components.

25. The method of claim 20, further comprising a thinning the selected substrate, wherein the thinning the selected substrate is performed subsequent to the coupling the second circuit layer to a second surface of the selected substrate, and prior to the coupling the buffer layer to a first surface of a selected substrate.

26. The method of claim 20, further comprising:

a) forming contact elements coupled to the first circuit layer; and

,

b) separating the ICs into dies, each die comprising an IC.

27. A method for forming integrated circuits (ICs) comprising a first circuit layer and a second circuit layer, comprising:

a) forming the first circuit layer on a first substrate;

b) separating the first circuit layer from the first substrate;

c) coupling the first circuit layer to a first surface of a selected substrate; and

,

d) forming the second circuit layer on a second surface of the selected substrate.

28. The method of claim 27 wherein the first substrate comprises a silicon substrate, and wherein the STEP of separating the first circuit layer from the first substrate comprises a process of thinning the silicon substrate.

29. The method of claim 27, wherein the selected substrate comprises a material selected from the following types of materials:

sapphire, quartz, silicon dioxide glass, aluminum nitride, hot-pressed silicon carbide ceramic, sintered silicon carbide ceramic, CVD silicon carbide, and alumina.

30. The method of claim 27, wherein the forming second circuit layer on a second surface of the selected substrate is performed prior to the coupling the first circuit layer to a first surface of a selected substrate.

31. A method for forming integrated circuits (ICs) comprising a first circuit layer and a second circuit layer, comprising:

a) forming the first circuit layer on a first substrate;

b) separating the first circuit layer from the first substrate;

c) forming the second circuit layer on a second substrate;

d) separating the second circuit layer from the second substrate;

e) coupling the first circuit layer to a first surface of a selected substrate; and

,

f) coupling the second circuit layer to a second surface of the selected substrate.

32. The method of claim 31 wherein the first substrate comprises a silicon substrate, and wherein the separating the first circuit layer from the first substrate comprises a process of thinning the silicon substrate.

33. The method of claim 31 wherein the first substrate comprises a silicon-on-insulator (SOI) substrate.

34. The method of claim 31, wherein the second substrate is selected from the following:

an SOI substrate, a silicon substrate having an insulating top layer, and a piezoelectric substrate.

35. The method of claim 31, wherein the selected substrate comprises a material selected from the following types of materials:

sapphire, quartz, silicon dioxide glass, aluminum nitride, hot-pressed silicon carbide ceramic, sintered silicon carbide ceramic, CVD silicon carbide, and alumina.

36. The method of claim 31, wherein the coupling the second circuit layer to a second surface of the selected substrate is performed prior to the coupling the first circuit layer to a first surface of a selected substrate.

37. A method for forming integrated circuits (ICs) comprising a first circuit layer and a second circuit layer, comprising:

a) forming the first circuit layer from an active layer of a silicon-on-sapphire (SOS) wafer, wherein the SOS wafer comprises the active layer and a sapphire substrate, and wherein the active layer is coupled to a first surface of the sapphire substrate; and

,

b) forming the second circuit layer on a second surface of the sapphire substrate.

38. An integrated circuit (IC), comprising:

a) a first circuit layer, coupled to a first surface of a selected substrate; and

,

b) a second circuit layer, coupled to a second surface of the selected substrate.

39. The IC of claim 38, wherein the selected substrate comprises a material selected from the following types of materials:

sapphire, quartz, silicon dioxide glass, aluminum nitride, hot-pressed silicon carbide ceramic, sintered silicon carbide ceramic, CVD silicon carbide, and alumina.

40. The IC of claim 38, wherein the second circuit layer comprises at least one of the following types of components:

active components, passive components, electro-optic components, microelectromechanical components, and acoustic wave components.

41. The IC of claim 38, further comprising:

a) contact elements operably coupled to the first circuit layer; and

,

b) contacts operably coupled to the second circuit layer.

42. The IC of claim 41, wherein the contact elements operably coupled to the first circuit layer are selected from the following types of contact elements:

solder bumps and copper pillars.

43. The IC of claim 42, wherein the contact elements operably coupled to the first circuit layer are operably coupled to first contacts of a package substrate by means of flip-chip mounting;

and wherein the contacts operably coupled to the second circuit layer are operably coupled to second contacts of the package substrate by means of wire bonds; and

wherein the first contacts of the package substrate and operably coupled to the second contacts of the package substrate by means of interconnects on the package substrate.

44. The IC of claim 38, wherein the first circuit layer comprises at least one of the following, an RF power amplifier circuit and an RF switch circuit, and wherein the second circuit layer comprises at least one of the following, an impedance matching circuit and an RF filter circuit.

45. An integrated circuit (IC), comprising:

a) a first circuit layer, formed on an active layer of an SOI substrate;

b) a buffer layer, wherein a first surface of the buffer layer is coupled to the active layer of the SOI substrate;

c) a selected substrate, wherein a first surface of the selected substrate is coupled to a second surface of the buffer layer; and

,

d) a second circuit layer coupled to a second surface of the selected substrate.

46. The IC of claim 45, wherein the selected substrate comprises a material selected from the following types of materials:

sapphire, quartz, silicon dioxide glass, aluminum nitride, hot-pressed silicon carbide ceramic, sintered silicon carbide ceramic, CVD silicon carbide, and alumina.

47. The IC of claim 45, wherein the second circuit layer comprises at least one of the following types of components:

active components, passive components, electro-optic components, microelectromechanical components, and acoustic wave components.

48. The IC of claim 45, further comprising:

a) contact elements operably coupled to the first circuit layer; and

,

b) contacts operably coupled to the second circuit layer.

49. The IC of claim 48, wherein the contact elements operably coupled to the first circuit layer are selected from the following types of contact elements:

solder bumps and copper pillars.

50. The IC of claim 49, wherein the contact elements operably coupled to the first circuit layer are operably coupled to first contacts of a package substrate by means of flip-chip mounting;

and wherein the contacts operably coupled to the second circuit layer are operably coupled to second contacts of the package substrate by means of wire bonds; and

wherein the first contacts of the package substrate are operably coupled to the second contacts of the package substrate by means of interconnects on the package substrate.

51. The IC of claim 45, wherein the first circuit layer comprises at least one of the following, an RF power amplifier circuit and an RF switch circuit, and wherein the second circuit layer comprises at least one of the following, an impedance matching circuit and an RF filter circuit.