Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP

• US 20130154108A1
• Filed: 12/14/2011
• Published: 06/20/2013
• Est. Priority Date: 12/14/2011
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Lin, Yaojian, Chen, Kang
• Granted Patent: US 8,592,992 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00

Abstract

A semiconductor device has a semiconductor die. An encapsulant is formed over the semiconductor die. A conductive micro via array is formed over the encapsulant outside a footprint of the semiconductor die. A first through-mold-hole having a step-through-hole structure is formed through the encapsulant to expose the conductive micro via array. In one embodiment, forming the conductive micro via array further includes forming an insulating layer over the encapsulant and the semiconductor die, forming a micro via array through the insulating layer outside the footprint of the semiconductor die, and forming a conductive layer over the insulating layer. In another embodiment, forming the conductive micro via array further includes forming a conductive ring. In another embodiment, an insulating layer is formed over the semiconductor die for structural support, a build-up interconnect structure is formed over the semiconductor die, and a conductive interconnect structure is formed within the first through-mold-hole.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming an encapsulant over the semiconductor die;

forming a conductive micro via array over the encapsulant outside a footprint of the semiconductor die; and

forming a first through-mold-hole (TMH) having a step-through-hole structure through the encapsulant to expose the conductive micro via array.

2. The method of claim 1, wherein forming the conductive micro via array further includes:

forming an insulating layer over the encapsulant and the semiconductor die;

forming a micro via array through the insulating layer outside the footprint of the semiconductor die; and

forming a conductive layer over the insulating layer.

3. The method of claim 1, wherein forming the conductive micro via array further includes forming a conductive ring.

4. The method of claim 1, wherein forming the first TMH further includes:

forming a second TMH partially through the encapsulant to a recessed surface of the encapsulant; and

forming a third TMH through the encapsulant within a footprint of the second TMH having a cross-sectional width less than a cross-sectional width of the second TMH and extending from the recessed surface of the encapsulant to the conductive micro via array.

5. The method of claim 1, forming an insulating layer over the semiconductor die for structural support.

6. The method of claim 1, further including forming a build-up interconnect structure over the semiconductor die.

7. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming an encapsulant over the semiconductor die; and

forming a conductive micro via array over the encapsulant outside a footprint of the semiconductor die.

8. The method of claim 7, further including forming a first through-mold-hole (TMH) having a step-through-hole structure through the encapsulant to expose the conductive micro via array.

9. The method of claim 8, wherein forming the first TMH further includes:

forming a second TMH partially through the encapsulant to a recessed surface of the encapsulant; and

forming a third TMH through the encapsulant within a footprint of the second TMH having a cross-sectional width less than a cross-sectional width of the second TMH and extending from the recessed surface of the encapsulant to the conductive micro via array.

10. The method of claim 8, further including forming a conductive interconnect structure within the first TMH.

11. The method of claim 7, wherein forming the conductive micro via array further includes:

forming an insulating layer over the encapsulant and the semiconductor die;

forming a micro via array through the insulating layer outside the footprint of the semiconductor die; and

forming a conductive layer over the insulating layer.

12. The method of claim 7, wherein forming the conductive micro via array further includes forming a conductive ring.

13. The method of claim 7, further including forming a build-up interconnect structure over the semiconductor die.

14. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming an encapsulant over the semiconductor die; and

forming a first through-mold-hole (TMH) having a step-through-hole structure through the encapsulant.

15. The method of claim 14, further including forming a conductive micro via array over the encapsulant outside a footprint of the semiconductor die.

16. The method of claim 15, wherein forming the conductive micro via array further includes:

forming an insulating layer over the encapsulant and the semiconductor die;

forming a micro via array through the insulating layer outside the footprint of the semiconductor die; and

forming a conductive layer over the insulating layer.

17. The method of claim 15, wherein forming the conductive micro via array further includes forming a conductive ring.

18. The method of claim 15, wherein forming the first TMH further includes:

forming a second TMH partially through the encapsulant to a recessed surface of the encapsulant; and

forming a third TMH through the encapsulant within a footprint of the second TMH having a cross-sectional width less than a cross-sectional width of the second TMH and extending from the recessed surface of the encapsulant to the conductive micro via array.

19. The method of claim 14, further including forming a conductive interconnect structure within the first TMH.

20. The method of claim 14, further including forming a build-up interconnect structure over the semiconductor die.

21. A semiconductor device, comprising:

a semiconductor die;

an encapsulant formed over the semiconductor die;

a conductive micro via array formed over the semiconductor die and the encapsulant outside a footprint of the semiconductor die; and

a first through-mold-hole (TMH) having a step-through-hole structure formed through the encapsulant to expose the conductive micro via array.

22. The semiconductor device of claim 21, further including:

an insulating layer formed over the semiconductor die and the encapsulant;

a micro via array formed through the insulating layer outside the footprint of the semiconductor die; and

a conductive layer formed over the insulating layer.

23. The semiconductor device of claim 21, wherein the conductive micro via array further includes a conductive ring.

24. The semiconductor device of claim 21, wherein the first TMH further includes:

a second TMH formed partially through the encapsulant to a recessed surface of the encapsulant; and

a third TMH formed through the encapsulant within a footprint of the second TMH having a cross-sectional width less than a cross-sectional width of the second TMH and extending from the recessed surface of the encapsulant to the conductive micro via array.

25. The semiconductor device of claim 21, further including a build-up interconnect structure formed over the semiconductor die.