VOLTAGE-TO-CURRENT SENSING CIRCUIT AND RELATED DC-DC CONVERTER

• US 20130154595A1
• Filed: 12/11/2012
• Published: 06/20/2013
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: Stmicroelectronics Design And Application S.R.O. (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Design And Application S.R.O. (STMicroelectronics NV)
• Inventors: Drinovsky, Martin
• Granted Patent: US 9,035,639 B2
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: G05F 1/561 Voltage to current converters amplifiers H03F
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators

Abstract

The present disclosure is directed to a voltage-to-current sensing circuit having a bias terminal configured to receive a reference voltage, an offset terminal configured to receive an offset current, and an operational amplifier configured to output a low voltage signal. The device includes a first amplifier having first and second high voltage inputs configured to receive a first voltage difference across a sense component on a high voltage line and to generate a first current, a second amplifier having first and second low voltage inputs configured to receive a second voltage difference between the bias terminal and the offset terminal and to generate a second current, a summing circuit configured to provide an intermediate voltage corresponding to a sum of the first and the second currents, and a low-voltage transistor coupled to an output of the amplifier and controlled by the intermediate voltage to generate the output current.

Claims

1. A device, comprising:

a voltage-to-current sensing circuit configured to generate an output current on a low-voltage line corresponding to a sense voltage on a high-voltage line, the sensing circuit having a bias terminal configured to receive a reference voltage, the sensing circuit including;

a four-input differential operational amplifier, including;

a low voltage output terminal;

a high-voltage input transconductance amplifier configured to receive the sense voltage and configured to generate a corresponding first current;

a low-voltage input transconductance amplifier configured to receive a comparison voltage and configured to generate a corresponding second current;

a summing circuit electrically coupled in cascade to said high-voltage and low-voltage input transconductance amplifiers and configured to generate an intermediate voltage corresponding to a sum of said first current and said second current;

a low-voltage transistor electrically coupled to the low voltage output terminal of said four-input differential operational amplifier, the low voltage transistor being configured to be controlled by said intermediate voltage, and being configured to generate said output current;

a comparison resistor configured to provide the comparison voltage, the comparison resistor being coupled between the bias terminal of the sensing circuit and a first terminal of said low-voltage transistor; and

an offset current generator coupled to said first terminal and configured to keep said low-voltage transistor in a conduction state when said sense voltage is null.

2. The device of claim 1 wherein the low-voltage transistor has a second terminal, further comprising a current mirror coupled to the second terminal of the low-voltage transistor and configured to generate a replica of said output current.

3. The device of claim 1, further comprising a generator configured to generate said reference voltage on said bias terminal of the sensing circuit.

4. The device of claim 1 wherein said summing circuit includes a low-voltage output transconductance amplifier coupled in cascade to said high-voltage and low-voltage input transconductance amplifiers, the low-voltage output transconductance amplifier being configured to generate the intermediate voltage corresponding to the sum of the first and second currents.

5. A device, comprising:

a single-phase DC-DC converter that includes;

a sense component;

a phase winding electrically coupled to the sense component, a voltage drop across the sense component being configured to represent a current flowing through the phase winding;

a voltage-to-current sensing circuit coupled to said sense component, the sensing circuit being configured to generate, on a low-voltage line, an output current that is configured to represent the current flowing through said phase winding, the sensing circuit including

a bias terminal configured to receive a reference voltage;

a four-input differential operational amplifier having a low voltage output, including;

a high-voltage input transconductance amplifier configured to receive a sense voltage from the sense component and configured to generate a corresponding first current;

a low-voltage input transconductance amplifier configured to receive a comparison voltage and configured to generate a corresponding second current;

summing circuit coupled in cascade to said high-voltage and low-voltage input transconductance amplifiers to generate an intermediate voltage corresponding to a sum of said first current and said second current;

a low-voltage transistor coupled to the low voltage output of said four-input differential operational amplifier, the low voltage transistor being configured to be controlled by said intermediate voltage, and being configured to generate said output current;

a comparison resistor configured to provide the comparison voltage, the comparison resistor being coupled between the bias terminal of the sensing circuit and a first terminal of said low-voltage transistor; and

an offset current generator coupled to said first terminal and configured to keep said low-voltage transistor in a conduction state when said sense voltage is null.

6. The device of claim 5 wherein the low-voltage transistor has a second terminal and a current mirror is coupled to the second terminal of the low-voltage transistor to generate a replica of said output current.

7. The device of claim 5, further comprising a generator configured to generate said reference voltage on said bias terminal of the sensing circuit.

8. The device of claim 5 wherein said summing circuit includes a low-voltage output transconductance amplifier coupled in cascade to said high-voltage and low-voltage input transconductance amplifiers, the low-voltage output transconductance amplifier being configured to generate the intermediate voltage corresponding to the sum of the first and second currents.

9. A device, comprising:

a multi-phase DC-DC converter, including;

a plurality of sense components;

a plurality of phase windings each coupled to a corresponding one of the sense components, each sense component being configured to provide a voltage drop corresponding to a current flowing through the corresponding phase winding;

a plurality of voltage-to-current sensing circuits each coupled to a corresponding one of the plurality of sense components, each sensing circuit being configured to generate an output current that represents the current flowing through said corresponding phase winding, each of the sensing circuits having a bias terminal, each of the bias terminals being coupled together, each sensing circuit including;

a four-input differential operational amplifier having a low voltage output, including;

a high-voltage input transconductance amplifier configured to receive a sense voltage across the associated sense component, and configured to generate a first current;

a low-voltage input transconductance amplifier configured to receive a comparison voltage and configured to generate a second current;

a summing circuit coupled in cascade to said high-voltage and low-voltage input transconductance amplifiers to generate an intermediate voltage corresponding to a sum of said first current and said second current;

a low-voltage transistor coupled to the low voltage output of said four-input differential operational amplifier, the low voltage transistor being configured to be controlled by said intermediate voltage, and being configured to generate said output current;

a comparison resistor configured to provide the comparison voltage, the comparison resistor being coupled between the bias terminal of the sensing circuit and a first terminal of said low-voltage transistor; and

an offset current generator coupled to said first terminal and configured to keep said low-voltage transistor in a conduction state when said sense voltage is null.

10. The device of claim 9 wherein the low-voltage transistor has a second terminal and a current mirror is coupled to the second terminal of the low-voltage transistor to generate a replica of said output current.

11. The device of claim 9, further comprising a generator configured to generate said reference voltage on said bias terminal of the sensing circuit.

12. The device of claim 9 wherein said summing circuit includes a low-voltage output transconductance amplifier coupled in cascade to said high-voltage and low-voltage input transconductance amplifiers, the low-voltage output transconductance amplifier being configured to generate the intermediate voltage corresponding to the sum of the first and second currents.

13. A device, comprising:

a voltage-to-current sensing circuit, the sensing circuit including;

a bias terminal configured to receive a reference voltage;

an offset terminal configured to receive an offset current;

an operational amplifier configured to output a low voltage signal, the operational amplifier including;

a first amplifier having first and second high voltage inputs that are configured to receive a first voltage difference across a sense component on a high voltage line, the first amplifier being configured to generate a first current;

a second amplifier having first and second low voltage inputs that are configured to receive a second voltage difference between the bias terminal and the offset terminal, the second amplifier being configured to generate a second current;

a summing circuit configured to provide an intermediate voltage corresponding to a sum of the first and the second currents; and

a low-voltage transistor coupled to an output of the operational amplifier, the low voltage transistor being configured to be controlled by the intermediate voltage, and being configured to generate the output current.

14. The device of claim 13, further comprising a current mirror coupled to the low-voltage transistor and configured to output the output current.

15. The device of claim 13, further comprising a reference voltage generator coupled to the bias terminal and configured to provide a reference voltage from a reference signal.