PHASE LOCK LOOP WITH ADAPTIVE LOOP BANDWIDTH

• US 20130154695A1
• Filed: 12/14/2011
• Published: 06/20/2013
• Est. Priority Date: 12/14/2011
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc., ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: Advanced Micro Devices, Inc., ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Abbasi, Saeed, Foxcroft, Michael R., Wong, Thomas Y.
• Granted Patent: US 8,610,473 B2
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

Wafer sort data can be converted to binary data, whereby each integrated circuit of the wafer is assigned a value of one or zero, depending on whether test data indicates the integrated circuit complies with a specification. In addition, each integrated circuit is assigned position data to indicate its position on the wafer. A frequency transform, such as a multidimensional discrete Fourier transform (DFT), is applied to the binary wafer sort data and position data to determine a spatial frequency spectrum that indicates error patterns for the wafer. The spatial frequency spectrum can be analyzed to determine the characteristics of the wafer formation process that resulted in the errors, and the wafer formation process can be modified to reduce or eliminate the errors.

Claims

1. A method, comprising:

adjusting a loop bandwidth of a phase lock loop (PLL) based on a difference between an output signal of the PLL and a reference signal of the PLL to lock the output signal to the reference signal.

2. The method of claim 1, wherein adjusting the loop bandwidth comprises changing a direct current (DC) open loop gain of the PLL based on the difference between the output signal and the reference signal.

3. The method of claim 1, wherein adjusting the loop bandwidth comprises changing a natural frequency of the PLL based on the difference between the output signal and the reference signal.

4. The method of claim 1, wherein the difference between the output signal and the reference signal comprises a phase difference.

5. The method of claim 1, wherein adjusting the loop bandwidth comprises changing a magnitude of a first current applied to a first node of the PLL based on the difference between the output signal and the reference signal.

6. The method of claim 5, wherein the first node comprises an input of a charge pump of the PLL.

7. The method of claim 5, wherein adjusting the loop bandwidth comprises changing a magnitude of a second current applied to a second node of the PLL based on the difference between the output signal and the reference signal.

8. The method of claim 7, wherein the first node comprises a first input of a charge pump of the PLL and the second node comprises a second input of the charge pump.

9. A method, comprising:

in response to determining a phase difference between an output signal of a phase lock loop (PLL) and a reference signal is in a first relationship to a threshold, setting a loop bandwidth of the PLL to a first level; and

in response to determining the phase difference between the output signal and the reference signal is in a second relationship to a threshold, setting a loop bandwidth of the PLL to a second level.

10. The method of claim 9, wherein the threshold is a reprogrammable value.

11. The method of claim 9, further comprising:

selecting a delay from a plurality of delays based on the threshold;

applying the delay to the output signal of the PLL to determine a delayed output signal; and

wherein determining the phase difference between the output signal and the reference signal comprises determining the phase difference based on a comparison

12. The method of claim 9, wherein:

setting the loop bandwidth to the first level comprises applying a current of a first magnitude to a first node of the PLL; and

setting the loop bandwidth to the second level comprises applying a current of a second magnitude to a second node of the PLL.

13. A device comprising a phase lock loop (PLL) having an adjustable loop bandwidth, the loop bandwidth based on a difference between an output signal of the PLL and a reference signal of the PLL.

14. The device of claim 13, wherein the PLL has an adjustable direct current (DC) open loop gain based on the difference between the output signal and the reference signal.

15. The device of claim 13, wherein the PLL has an adjustable natural frequency based on the difference between the output signal and the reference signal.

16. The device of claim 13, wherein the difference between the output signal and the reference signal comprises a phase difference.

17. The device of claim 13, wherein the PLL comprises a charge pump including a first output to provide a first current, a magnitude of the first current based on the difference between the output signal and the reference signal.

18. The device of claim 17 further comprising an active filter comprising a first input coupled to the first output of the charge pump.

19. The device of claim 17, wherein the charge pump comprises a second output to provide a second current, a magnitude of the second current based on the difference between the output signal and the reference signal.

20. The device of claim 19, further comprising a voltage controlled oscillator coupled to the first output and the second output of the charge pump.