VOLTAGE LEVEL SHIFTER

• US 20130154713A1
• Filed: 09/06/2012
• Published: 06/20/2013
• Est. Priority Date: 12/16/2011
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Wang, Meng
• Granted Patent: US 8,686,784 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A level shifter includes a latch supplied at a first voltage, and first and second series connections of first and second switch elements and first and second biased elements in series with first and second branches of the latch respectively. Third and fourth switch elements are connected in parallel with the first and second series connections respectively. The input signal, at a voltage different from the first voltage, activates the third or fourth switch element during a transition period after a change of state of the input signal one way or the other to change the state of the latch, and deactivates the third or fourth switch element and activates the first or second switch element to maintain the state of the latch during a stabilization period following the transition period. The transition periods are shortened, reducing current consumption and transfer delay times.

Claims

1. A level shifter, comprising:

a latch supplied at a first voltage and having first and second branches;

first and second switch elements, respectively connected in series with said first and second branches;

an output connected to at least one of said branches;

third and fourth switch elements, respectively connected in parallel with said first and second series connections; and

a controller receiving an input signal at a voltage different from said first voltage for activating said third switch element during a transition period after assertion of said input signal to change the state of said latch, and for deactivating said third switch element and activating said first switch element to maintain the state of said latch during a stabilization period following said transition period, for activating said fourth switch element during an inverse transition period after de-assertion of said input signal to change the state of said latch, and for deactivating said fourth switch element and activating said second switch element to maintain the state of said latch during a stabilization period following said inverse transition period.

2. The level shifter of claim 1, further comprising first and second biased elements, respectively connected in series between said first and second switch elements and said first and second branches, wherein said first and second biased elements are biased by a second voltage that is less than said first voltage.

3. The level shifter of claim 1, wherein said controller comprises a capacitive timing element defining a duration of said transition period and said inverse transition period.

4. The level shifter of claim 1, wherein said controller comprises a gate element defining a start of said stabilization period as a function of ends of said transition period and said inverse transition period.

5. The level shifter of claim 1, further comprising:

a charge pump that supplies power to the level shifter; and

a power transistor having a gate electrode connected to said output of the level shifter, wherein said output applies a voltage to the gate electrode of the power transistor.

6. A level shifter, comprising:

a latch having first and second branches supplied at a first voltage;

a first series connection having a first biased element connected in series with said first branch and a first switch element connected in series with said first biased element;

a second series connection of a second biased element connected in series with said second branch and a second switch element connected in series with said first biased element;

wherein said first and second biased elements are biased by a second voltage that is less than said first voltage;

an output connected to at least one of said branches;

third and fourth switch elements, respectively connected in parallel with said first and second series connections; and

a controller for receiving an input signal at a voltage different from said first voltage for activating said third switch element during a transition period after assertion of said input signal to change the state of said latch, and for deactivating said third switch element and activating said first switch element to maintain the state of said latch during a stabilization period following said transition period, for activating said fourth switch element during an inverse transition period after de-assertion of said input signal to change the state of said latch, and for deactivating said fourth switch element and activating said second switch element to maintain the state of said latch during a stabilization period following said inverse transition period.

7. The level shifter of claim 6, wherein said controller includes a capacitive timing element that defines a duration of said transition period and said inverse transition period.

8. The level shifter of claim 7, wherein said controller includes a gate element that defines a start of said stabilization period as a function of ends of said transition period and said inverse transition period.

9. A level shifter, comprising:

a latch having first and second branches supplied at a first voltage;

a first series connection having a first biased transistor having a signal path that is connected in series with said first branch and a first switch transistor having a signal path that is connected in series between said signal path of said first biased transistor and ground;

a second series connection of a second biased transistor having a signal path that is connected in series with said second branch and a second switch transistor having a signal path that is connected in series between said signal path of said first biased transistor and ground;

wherein said first and second biased transistors have gate electrodes biased by a second voltage that is less than said first voltage;

an output connected to at least one of said branches;

third and fourth switch transistors having signal paths that are connected in parallel with said first and second series connections respectively; and

a controller receiving an input signal at a voltage different from said first voltage for applying voltages to gate electrodes of said first, second, third and fourth switch transistors, activating said third switch transistor during a transition period after assertion of said input signal to change the state of said latch, deactivating said third switch transistor and activating said first switch transistor to maintain the state of said latch during a stabilization period following said transition period, activating said fourth switch transistor during an inverse transition period after de-assertion of said input signal to change the state of said latch, and deactivating said fourth switch transistor and activating said second switch transistor to maintain the state of said latch during a stabilization period following said inverse transition period.

10. The level shifter of claim 9, wherein said controller includes:

a capacitive timing transistor defining a duration of said transition period and said inverse transition period; and

a gate element defining a start of said stabilization period as a function of ends of said transition period and said inverse transition period.