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POWER LAYER GENERATION OF INVERTER GATE DRIVE SIGNALS

  • US 20130155746A1
  • Filed: 02/14/2013
  • Published: 06/20/2013
  • Est. Priority Date: 07/16/2010
  • Status: Active Grant
First Claim
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1. A system for controlling operation of power inverter switches, comprising:

  • control circuitry configured to generate gate timing-related signals for timing of state changes of the switches;

    a plurality of inverters coupled to the control circuitry in parallel, the output of the inverters being coupled to provide a common 3-phase output, each inverter comprising power layer circuitry and a plurality of solid state switches coupled to the power layer circuitry; and

    a plurality of data conductors, one data conductor coupled between the control circuitry the power layer circuitry of each inverter for conveying the gate timing-related signals from the control circuitry to the respective power layer circuitry;

    wherein power layer circuitry of each inverter is configured to receive the gate timing-related signals and to recompute the timing for the state changes based upon the received gate timing-related signals to control state changes of the solid state switches of the respective inverter to convert input power to controlled output power based upon the recomputed timing; and

    wherein the control circuitry is configured to periodically transmit synchronization signals to the power layer circuitry of each inverter and the power layer circuitry of each inverter is configured to adjust a respective power layer clock between the synchronization signals to compensate for variability in an operating frequency of an oscillator upon which the power layer clock is based.

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