POWER LAYER GENERATION OF INVERTER GATE DRIVE SIGNALS

• US 20130155746A1
• Filed: 02/14/2013
• Published: 06/20/2013
• Est. Priority Date: 07/16/2010
• Status: Active Grant

• Current Assignee: Rockwell Automation Technologies Incorporated (Rockwell Automation, Inc.)
• Original Assignee: Rockwell Automation Technologies Incorporated (Rockwell Automation, Inc.)
• Inventors: Campbell, Alan J., Radosevich, Richard H.
• Granted Patent: US 8,675,376 B2
• Time in Patent Office: Days
• US Class Current: 363/131
• CPC Class Codes: H02M 7/537 using semiconductor devices only, e.g. single switched pulse inverters
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

Techniques include systems and methods of synchronizing multiple parallel inverters in a power converter system. In one embodiment, control circuitry is connected to a power layer interface circuitry at each of the parallel inverters, via an optical fiber interface. The system is synchronized by transmitting a synchronizing pulse to each of the inverters. Depending on the operational mode of the system, different data exchanges may occur in response to the pulse. In an off mode, power up and power down data may be exchanged between the control circuitry and the inverters. In an initiating mode, identification data may be transmitted from the inverters to the control circuitry. In an active mode, control data may be sent from the control circuitry to the inverters. In some embodiments, the inverters also transmit feedback data and/or acknowledgement signals to the control circuitry. Power layer circuitry of the inverter adjusts a local clock based upon sampled data from the control circuitry to maintain synchronicity of the inverters between synchronization pulses.

Claims

1. A system for controlling operation of power inverter switches, comprising:

control circuitry configured to generate gate timing-related signals for timing of state changes of the switches;

a plurality of inverters coupled to the control circuitry in parallel, the output of the inverters being coupled to provide a common 3-phase output, each inverter comprising power layer circuitry and a plurality of solid state switches coupled to the power layer circuitry; and

a plurality of data conductors, one data conductor coupled between the control circuitry the power layer circuitry of each inverter for conveying the gate timing-related signals from the control circuitry to the respective power layer circuitry;

wherein power layer circuitry of each inverter is configured to receive the gate timing-related signals and to recompute the timing for the state changes based upon the received gate timing-related signals to control state changes of the solid state switches of the respective inverter to convert input power to controlled output power based upon the recomputed timing; and

wherein the control circuitry is configured to periodically transmit synchronization signals to the power layer circuitry of each inverter and the power layer circuitry of each inverter is configured to adjust a respective power layer clock between the synchronization signals to compensate for variability in an operating frequency of an oscillator upon which the power layer clock is based.

2. The system of claim 1, wherein substantially identical gate timing-related signals are transmitted to the power layer circuitry of all inverters at substantially the same time.

3. The system of claim 1, wherein the power layer circuitry of each inverter is configured to adjust the respective power layer clock based upon data sampled from the timing-related signals transmitted by the control circuitry.

4. The system of claim 3, wherein the power layer circuitry of each inverter is configured to adjust the respective power layer clock based upon a number of data bits sampled between transition bits in the sampled data.

5. The system of claim 1, wherein the power layer circuitry of each inverter is configured to acknowledge receipt of the synchronization signal.

6. The system of claim 5, wherein in the event of failure of the power layer circuitry of any inverter to acknowledge receipt of the synchronization signal, the control circuitry is configured to command the power layer circuitry of all inverters to operate on the basis of previous gate timing-related signals.

7. The system of claim 1, wherein the control circuitry is configured to generate a control event signal for synchronizing events in one or more operational modes of the system, and wherein the power layer circuitry of each inverter is configured to receive the control event signal and to communicate with the control circuitry based on the control event signal and based on one of a plurality of operational modes of the system.

8. A system for controlling operation of a power inverter, comprising:

control circuitry configured to generate a control event signal for synchronizing events in one or more operational modes of the system;

a data conductor coupled to the control circuitry for conveying the signals to and from the control circuitry;

power layer circuitry coupled to the data conductor and configured to receive the control event signal and to communicate with the control circuitry via the data conductor based on the control event signal and based on the operational mode of the system; and

a plurality of solid state switches coupled to the power layer circuitry and configured to change state to convert input power to controlled output power based on the control event signal and based on the operational mode of the system.

9. The system of claim 8, wherein the control event signal comprises a sync cycle comprising one rising edge and one falling edge approximately 6 μ

s following the one rising edge.

10. The system of claim 8, wherein the data conductor comprises two optical fibers.

11. The system of claim 10, wherein a first optical fiber is dedicated to transmitting signals from the control circuitry to the power layer circuitry, and a second optical fiber is dedicated to transmitting signals from the power layer circuitry to the control circuitry.

12. The system of claim 11, wherein the power layer circuitry transmits, over the second optical fiber, at least signals representative of power phase current.

13. The system of claim 12, wherein the power layer circuitry also transmits, over the second optical fiber, signals representative of at least one of temperature, bus voltage, and fault status.

14. The system of claim 11, wherein the one or more operational modes comprises an off mode, and wherein the control circuitry is configured to transmit a sync pulse to the power layer circuitry and configured to receive power down data from the power layer circuitry during the off mode.

15. The system of claim 11, wherein the one or more operational modes comprises an initializing mode, and wherein the control circuitry is configured to transmit a sync pulse to the power layer circuitry and configured to receive identification data from the power layer circuitry during the initializing mode.

16. The system of claim 15, wherein the control circuitry is further configured to transmit thermal parameter data to the power layer circuitry during the initializing mode.

17. The system of claim 11, wherein the one or more operational modes comprises an active mode, and wherein the control circuitry transmits a sync pulse and control data to the power layer circuitry during the active mode.

18. The system of claim 17, wherein the control circuitry receives an acknowledgement signal from the power layer circuitry following the transmitted control data during the active mode.

19. The system of claim 17, wherein the control circuitry is further configured to transmit thermal parameter data to the power layer circuitry during the active mode.

20. The system of claim 19, wherein the power layer circuitry is further configured to transmit a thermal feedback signal to the control circuitry in response to the thermal parameter data transmitted from the control circuitry.

21. The system of claim 17, wherein the control data comprises encoded data and timing information, and wherein the power layer circuitry is configured to recompute timing information from the control data to drive the plurality of solid state switches.