STORAGE DEVICE

• US 20130155790A1
• Filed: 12/10/2012
• Published: 06/20/2013
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Atsumi, Tomoaki
• Granted Patent: US 9,990,965 B2
• Time in Patent Office: Days
• US Class Current: 365/189.011
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits

Abstract

Noise attributed to signals of a word line, in first and second bit lines which are overlapped with the same word line in memory cells stacked in a three-dimensional manner is reduced in a storage device with a folded bit-line architecture. The storage device includes a driver circuit including a sense amplifier, and first and second memory cell arrays which are stacked each other. The first memory cell array includes a first memory cell electrically connected to the first bit line and a first word line, and the second memory cell array includes a second memory cell electrically connected to the second bit line and a second word line. The first and second bit lines are electrically connected to the sense amplifier in the folded bit-line architecture. The first word line, first bit line, second bit line, and second word line are disposed in this manner over the driver circuit.

Claims

1. A semiconductor device comprising:

a driver circuit comprising a sense amplifier, the sense amplifier being electrically connected to a first bit line and a second bit line;

a first memory cell array comprising a first memory cell, the first memory cell being electrically connected to the first bit line and a first word line; and

a second memory cell array comprising a second memory cell over the first memory cell array, the second memory cell being electrically connected to the second bit line and a second word line,

wherein the first bit line is provided over the first word line,

wherein the second word line is provided over the second bit line, and

wherein the first memory cell overlaps with the second memory cell.

2. The semiconductor device according to claim 1, wherein the first memory cell array is provided over the driver circuit.

3. The semiconductor device according to claim 2, wherein the driver circuit comprises a transistor comprising a channel formation region in a single-crystal semiconductor substrate.

4. The semiconductor device according to claim 1, wherein each of the first memory cell and the second memory cell comprises a transistor comprising an oxide semiconductor layer having a channel region.

5. The semiconductor device according to claim 4, wherein the oxide semiconductor layer comprises indium, zinc, and one or more metal elements selected from gallium, tin, hafnium, aluminum, and zirconium.

6. A semiconductor device comprising:

a driver circuit comprising a sense amplifier, the sense amplifier being electrically connected to a first bit line and a second bit line;

a first memory cell array comprising a first memory cell comprising a first transistor, the first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first semiconductor layer, wherein one of the first source electrode and the first drain electrode is electrically connected to the first bit line, and the first gate electrode is electrically connected to a first word line; and

a second memory cell array comprising a second memory cell comprising a second transistor, the second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second semiconductor layer, wherein the one of the second source electrode and the second drain electrode is electrically connected to the second bit line, and the second gate electrode is electrically connected to a second word line,

wherein the first bit line is provided over the first word line,

wherein the second word line is provided over the second bit line, and

wherein the first memory cell overlaps with the second memory cell.

7. The semiconductor device according to claim 6, wherein the first memory cell array is provided over the driver circuit.

8. The semiconductor device according to claim 7, wherein the driver circuit comprises a third transistor comprising a channel formation region in a single-crystal semiconductor substrate.

9. The semiconductor device according to claim 6, wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor.

10. The semiconductor device according to claim 9, wherein the oxide semiconductor comprises indium, zinc, and one or more metal elements selected from gallium, tin, hafnium, aluminum, and zirconium.

11. A semiconductor device comprising:

a driver circuit comprising a sense amplifier, the sense amplifier being electrically connected to a first bit line and a second bit line;

a first memory cell array comprising a first memory cell comprising a first transistor, the first transistor comprising;

a first semiconductor layer;

a first source electrode and a first drain electrode over the first semiconductor layer, one of the first source electrode and the first drain electrode being electrically connected to the first bit line,

a first insulating layer over the first source electrode, the first drain electrode, and the first semiconductor layer; and

a first gate electrode over the first insulating layer, the first gate electrode being electrically connected to a first word line; and

a second memory cell array comprising a second memory cell comprising a second transistor, the second transistor comprising;

a second semiconductor layer;

a second source electrode and a second drain electrode over the second semiconductor layer, one of the second source electrode and the second drain electrode being electrically connected to the second bit line,

a second insulating layer over the second source electrode, the second drain electrode, and the second semiconductor layer; and

a second gate electrode over the second insulating layer, the second gate electrode being electrically connected to a second word line,

wherein the first bit line is provided over the first word line,

wherein the second word line is provided over the second bit line, and

wherein the first memory cell overlaps with the second memory cell.

12. The semiconductor device according to claim 11, wherein the first memory cell array is provided over the driver circuit.

13. The semiconductor device according to claim 12, wherein the driver circuit comprises a third transistor comprising a channel formation region in a single-crystal semiconductor substrate.

14. The semiconductor device according to claim 11, wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor.

15. The semiconductor device according to claim 14, wherein the oxide semiconductor comprises indium, zinc, and one or more elements selected from gallium, tin, hafnium, aluminum, and zirconium.