SELECTING A MASTER PROCESSOR FROM AN AMBIGUOUS PEER GROUP

• US 20130155841A1
• Filed: 12/15/2011
• Published: 06/20/2013
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Engebretsen, David R., Knight, Stephen A., Lange-Pearson, Adam C., Saley, Jaimeson J.
• Granted Patent: US 8,953,489 B2
• Time in Patent Office: Days
• US Class Current: 370/218
• CPC Class Codes: H04L 41/0803 Configuration setting
• CPC Class Codes: H04L 41/12 Discovery or management of network topologies
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 67/1051 Group master selection mechanisms

Abstract

A distributed switch may include a plurality of special-purpose processors that control the different functions of the switch. To enable some special services, however, the distributed switch may need one of these processors to perform the role of a master. When a processor is powered on, the processor may publish a corresponding unique ID. Before electing the master, the special-purpose processors may use a discovery process to identify the network topology of the switch and evaluate the published IDs to determine which processor should be the master. If all the processors nominate the same master processor, then that processor is elected as the master and may finish configuring the distributed switch to enable the special services.

Claims

1-7. -7. (canceled)

8. A computer program product for electing a master processor from a plurality of processors, the computer program product comprising:

a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code comprising computer-readable program code configured to;

store in a first portion of a shared memory a first unique identifier for a first processor of the plurality of processors, wherein the shared memory is accessible by the plurality of processors via a network fabric;

traverse the network fabric comprising the plurality of processors;

read, from a second portion of the shared memory, a second unique identifier for a second processor of the plurality of processors;

determine, based on one or more criteria, a nominee identifier from among the first and second unique identifiers;

store the nominee identifier in a register in the first portion of the shared memory, wherein the nominee identifier is read from the register by one of the plurality of processors; and

elect the master processor that corresponds to the nominee identifier.

9. The computer program product of claim 8, wherein electing the master processor that corresponds to the nominee identifier further comprises computer-readable program code configured to:

after storing the nominee identifier in the register, determine whether the second portion of the shared memory contains the same nominee identifier;

if so, elect the master processor that corresponds to the same nominee identifier; and

otherwise, determine whether a different unique identifier stored in the second portion of the shared memory better satisfies the one or more criteria than the nominee identifier.

10. The computer program product of claim 9, further comprising computer-readable program code configured to, if the different unique identifier better satisfies the one or more criteria than the nominee identifier:

re-traversing the network fabric to identify a third processor of the plurality of processors, wherein the third processor stores a third unique identifier in a third portion of the shared memory; and

determining, based on the one or more criteria, a different nominee identifier from among the first, second, and third unique identifiers.

11. The computer program product of claim 8, wherein the first and second portions of the shared memory are distributed such that each portion is uniquely located on separate hardware components.

12. The computer program product of claim 11, wherein at least two of the plurality of processors are located on separate hardware components.

13. The computer program product of claim 11, wherein the first portion of the shared memory and the first processor are both located on one of the separate hardware components, wherein, before the master processor is elected, only the first processor is permitted to write data to the first portion of the shared memory.

14. A system for electing a master processor from a plurality of processors, comprising:

a first processor of the plurality of processors;

a second processor of the plurality of processors;

a shared memory that is accessible by the plurality of processors via a network fabric, the shared memory comprising;

a first portion storing a first unique identifier for the first processor, and

a second portion storing a second unique identifier for the second processor,

wherein the first processor is configured to read from the second portion the second unique identifier and determine, based on one or more criteria, a nominee identifier from among the first and second unique identifiers,

wherein the first processor is configured to store the nominee identifier in a register in the first portion of the shared memory, wherein the nominee identifier is read from the register by one of the plurality of processors, and

wherein at least one of the plurality of processors elect the master processor that corresponds to the nominee identifier.

15. The system of claim 14, wherein electing the master processor that corresponds to the nominee identifier further comprises:

after storing the nominee identifier in the register, the first processor is configured to determine whether the second portion of the shared memory contains the same nominee identifier;

if so, the first processor is configured to elect the master processor that corresponds to the same nominee identifier; and

otherwise, the first processor is configured to determine whether a different unique identifier stored in the second portion of the shared memory better satisfies the one or more criteria than the nominee identifier.

16. The system of claim 15, further comprising, if the different unique identifier better satisfies the one or more criteria than the nominee identifier:

the first processor is configured to re-traverse the network fabric to identify a third processor of the plurality of processors, wherein the third processor stores a third unique identifier in a third portion of the shared memory; and

the first processor is configured to determine, based on the one or more criteria, a different nominee identifier from among the first, second, and third unique identifiers.

17. The system of claim 14, wherein the first and second portions of the shared memory are distributed such that each portion is uniquely located on separate hardware components.

18. The system of claim 17, wherein at least two of the plurality of processors are located on separate hardware components.

19. The system of claim 17, wherein the first portion of the shared memory and the first processor are both located on one of the separate hardware components, wherein, before the master processor is elected, only the first processor is permitted to write data to the first portion of the shared memory.

20. The system of claim 14, further comprising:

upon determining that the elected master processor fails, the plurality of processors are configured to elect a new master processor.