Composite wafer for fabrication of semiconductor devices

• US 20130157440A1
• Filed: 12/15/2011
• Published: 06/20/2013
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Koudymov, Alexei, Ramdani, Jamal, Swaminathan, Kierthi
• Granted Patent: US 8,940,620 B2
• Time in Patent Office: Days
• US Class Current: 438/464
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: Y10T 428/2495 Thickness [relative or absolute]

Abstract

A composite wafer includes a first substrate having a first vertical thickness and a top surface, the top surface being prepared in a state for subsequent semiconductor material epitaxial deposition. A carrier substrate is disposed beneath the first substrate. The carrier substrate has a second vertical thickness greater than the first vertical thickness. An interlayer bonds the first substrate to the carrier substrate.

Claims

1. A composite wafer comprising:

a first substrate having a first vertical thickness and a top surface, the top surface being prepared in a state for subsequent semiconductor material epitaxial deposition;

a carrier substrate disposed beneath the first substrate, the carrier substrate having a second vertical thickness greater than the first vertical thickness; and

an interlayer that bonds the first substrate to the carrier substrate.

3. The composite wafer of claim 1 wherein the second thickness is approximately 400 μ

m thick or greater.

4. The composite wafer of claim 1 wherein the first substrate comprises sapphire.

5. The composite wafer of claim 1 wherein the carrier substrate is selected from the group consisting of sapphire, silicon, silicon carbide, diamond, gallium nitride, aluminum nitride, boron nitride, and zinc oxide.

2. The composite wafer of claim wherein the first thickness in an approximate range of 100-200 μ

m thick.

6. The composite wafer of claim wherein the state of the top surface is polished.

7. A method comprising:

(a) bonding a bottom surface of a first substrate to a top surface of a carrier substrate, the first substrate also having a top surface, a first thickness, and being of a first semiconductor material type, the carrier substrate being of a second semiconductor material type and having a second thickness greater than the first thickness;

(b) forming one or more nitride layers on over the top surface of the first substrate;

(c) fabricating nitride-based semiconductor devices in the one or more nitride layers; and

(d) de-bonding the top surface of the carrier substrate from the bottom surface of the first substrate.

9. The method of claim 7 wherein the bonding step comprises forming an interlayer between the first substrate and the carrier substrate that bonds the top surface of the carrier substrate to the bottom surface of the first substrate.

10. The method of claim 9 wherein the interlayer comprises silicon dioxide.

11. The method of claim 7 wherein the first substrate comprises sapphire and the first thickness is in an approximate range of 100-200 μ

m thick.

12. The method of claim 7 wherein the second thickness is approximately 400 μ

m thick or greater.

13. The method of claim 7 wherein the carrier substrate is selected from the group consisting of sapphire, silicon, silicon carbide, diamond, gallium nitride, aluminum nitride, boron nitride, and zinc oxide.

14. The method of claim 7 wherein the de-bonding step comprises performing a wet etch in a chemical solution

15. The method of claim 7 wherein the nitride-based semiconductor devices are formed on individual dies of a wafer, and further comprising separating the individual dies prior to the de-bonding step.

17. The method of claim 7 further comprising polishing the top surface of the first substrate prior to forming the one or more nitride layers.

18. The method of claim 17 wherein the polishing of the top surface results in an atomically-flat top surface.

21. The method of claim 7 wherein the bonding comprises adhesively affixing the first substrate to the carrier substrate.

22. The method of claim 7 wherein the first and second semiconductor material types have respective first and second coefficients of thermal expansion that are substantially matched to one another.

23. The method of claim 7 wherein the first semiconductor material type is selected from a group consisting of sapphire, diamond, gallium nitride, aluminum nitride, boron nitride, silicon carbide, and zinc oxide.

24. The method of claim 7 wherein the second semiconductor material type is selected from a group consisting of silicon and sapphire.

28. The method of claim 7 wherein the nitride-based semiconductor devices are fabricated as a plurality of die, and wherein the de-bonding comprises:

individuating each of the die; and

for each of the individuated die, de-bonding the first substrate from the carrier substrate.

8. (canceled)

16. The method of claim 8 wherein the nitride-based semiconductor devices are formed on individual dies of a wafer, and further comprising separating the individual dies after the de-bonding step.

19-20. -20. (canceled)

25-26. -26. (canceled)