SEMICONDUCTOR DEVICE INCLUDING POLYSILICON RESISTOR AND METAL GATE RESISTOR AND METHODS OF FABRICATING THEREOF

• US 20130157452A1
• Filed: 12/16/2011
• Published: 06/20/2013
• Est. Priority Date: 12/16/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsieh, Tung-Heng, Yu, Kuo-Feng, Hou, Chin-Shan, Lin, Shyue-Shyh, Chen, Jian-Hao, Lu, Chia-Yu, Lin, Hsien-Chin
• Granted Patent: US 9,070,624 B2
• Time in Patent Office: Days
• US Class Current: 438/589
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.

Claims

1. A method, comprising:

providing a semiconductor substrate;

forming a first gate structure on the semiconductor substrate;

forming a sacrificial gate structure on the semiconductor substrate adjacent the first gate structure; and

forming a dielectric layer overlying the first gate structure and the sacrificial gate structure, wherein the dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness above a top surface of the sacrificial gate structure, wherein the second thickness is less than the first thickness.

2. The method of claim 1, further comprising:

planarizing the dielectric layer overlying the first gate structure and the sacrificial gate structure, wherein the planarizing removes the dielectric layer above the sacrificial gate structure.

3. The method of claim 2, wherein a portion of the dielectric layer remains on the top surface of the first gate structure during and after the planarizing.

4. The method of claim 1, wherein the forming the first gate structure and the forming the sacrificial gate structure includes:

forming a layer of polysilicon;

forming a masking element on the layer of polysilicon; and

etching the layer of polysilicon using the masking element to form the first gate structure and the sacrificial gate structure.

5. The method of claim 4, wherein the forming the first gate structure and the forming the sacrificial gate structure further includes:

depositing a layer of gate dielectric material underlying the layer of polysilicon; and

etching the layer of gate dielectric material using the masking element to form the first gate structure and the sacrificial gate structure.

6. The method of claim 4, further comprising:

doping the layer of polysilicon.

7. The method of claim 6, wherein the doping is performed while the masking element is disposed on the layer of polysilicon and prior to the etching of the layer of polysilicon.

8. The method of claim 1, wherein the first thickness is greater than the second thickness by at least approximately 25 nanometers.

9. A method, comprising:

providing a substrate having a first surface;

forming a recess in the substrate, thereby providing a recessed region having a second surface spaced a distance from the first surface;

forming a polysilicon gate structure in the recess on the second surface;

forming a sacrificial gate structure on the first surface; and

forming a dielectric layer overlying the polysilicon gate structure and the sacrificial gate structure.

10. The method of claim 9, wherein the forming the recess includes forming a recess in an isolation region of the substrate.

11. The method of claim 9, wherein the forming the recess includes forming a recess in a plurality of isolation regions, wherein the plurality of isolation regions are interposed by an active region.

12. The method of claim 9, further comprising:

planarizing the dielectric layer until a top surface of the sacrificial gate structure is exposed and a portion of the dielectric layer remains overlying the polysilicon gate structure.

13. The method of claim 12, further comprising:

after planarizing the dielectric layer, removing the sacrificial gate structure to form an opening; and

forming a metal gate electrode in the opening.

14. The method of claim 9, wherein the recess is greater than approximately 25 nm in depth.

15. The method of claim 9, further comprising:

forming a contact etch stop layer (CESL) on the polysilicon gate structure and the sacrificial gate structure, wherein the CESL underlies the dielectric layer.

16. A method, comprising:

providing a substrate having a polysilicon layer;

etching a recess in the polysilicon layer to provide a first portion having a first thickness and a second portion having a second thickness, the second thickness being less than the first thickness;

after etching the polysilicon layer, patterning the polysilicon layer to form a first gate structure and a second gate structure, wherein the first gate structure is formed in the first portion of the polysilicon and the second gate structure is formed in the second portion of the polysilicon layer;

removing the first gate structure to form an opening; and

forming a metal gate structure in the opening.

17. The method of claim 16, further comprising:

doping the polysilicon layer prior to etching the recess in the polysilicon layer, wherein the doping creates a boron-rich second portion of the polysilicon layer.

18. The method of claim 17, wherein etching the recess includes using the boron-rich second portion of the polysilicon layer as an etch stop.

19. The method of claim 16, wherein the second thickness is between approximately 25 nanometers and approximately 80 nanometers less than the first thickness.

20. The method of claim 16, further comprising:

forming an inter-layer dielectric (ILD) layer on the first and second gate structures, wherein the ILD layer has a third thickness above the first gate structure and a fourth thickness above the second gate structure, the fourth thickness being greater that the third thickness.