CONTROL SYSTEM AND RELAY APPARATUS

• US 20130159585A1
• Filed: 11/01/2012
• Published: 06/20/2013
• Est. Priority Date: 12/20/2011
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: OGAWA, Yuichi, KAWAGOE, Nobuyoshi
• Granted Patent: US 9,111,052 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers

Abstract

A bus interface receives, via a bus, a control signal for controlling an electronic circuit, and outputs a signal corresponding to the received control signal to the electronic circuit. A signal maintaining circuit maintains the value of the signal to be output from the bus interface to the electronic circuit in accordance with an instruction from a reset control circuit. When the bus becomes unusable due to termination of operations of the control device or the like, the reset control circuit causes the signal maintaining circuit to maintain the value of the output signal to the electronic circuit, and subsequently resets the bus interface so as to restore the bus.

Claims

1. A control system comprising:

an electronic circuit;

a bus interface configured to receive, via a bus, a control signal for controlling the electronic circuit, and output a signal corresponding to the received control signal to the electronic circuit;

a signal maintaining circuit configured to maintain a value of the signal to be output from the bus interface to the electronic circuit;

a reset control circuit configured to cause the signal maintaining circuit to maintain the value of the output signal to the electronic circuit, and subsequently reset the bus interface; and

a control device configured to control the electronic circuit by outputting the control signal via the bus.

2. The control system according to claim 1,

wherein the control device includes

a first control device;

and

a second control device configured to,

upon detecting that operations of the first control device have been terminated, output a reset instruction via a reset signal line, and subsequently control the electronic circuit in place of the first control device; and

wherein the reset control circuit is configured to, upon receiving the reset instruction via the reset signal line, cause the signal maintaining circuit to maintain the value of the output signal to the electronic circuit, and subsequently reset the bus interface.

3. The control system according to claim 2, wherein the bus interface is configured to, after being reset by the reset control circuit, output again to the signal maintaining circuit a value of a signal being output from the signal maintaining circuit to the electronic circuit, in accordance with an instruction from the second control device via the bus.

4. The control system according to claim 3, wherein the bus interface is configured to output again to the signal maintaining circuit the value of the signal being output from the signal maintaining circuit to the electronic circuit, by loading the value of the signal being output from the signal maintaining circuit to the electronic circuit and outputting the loaded value of the signal to the signal maintaining circuit.

5. The control system according to claim 3, wherein after the bus interface has output again to the signal maintaining circuit the value of the signal being output from the signal maintaining circuit to the electronic circuit, the reset control circuit releases the signal maintaining circuit from a state of maintaining the value of the output signal to the electronic circuit.

6. The control system according to claim 5,

wherein the second control device is configured to instruct the bus interface via the bus to output again to the signal maintaining circuit the value of the signal being output from the signal maintaining circuit to the electronic circuit, and subsequently transmit to the bus interface via the bus a release instruction for releasing the signal maintaining circuit from the state of maintaining the value of the output signal;

and

wherein the reset control circuit is configured to, in response to reception of the release instruction by the bus interface, release the signal maintaining circuit from the state of maintaining the value of the output signal to the electronic circuit.

7. The control system according to claim 1, wherein the signal maintaining circuit is configured to maintain, as the signal to be output from the bus interface to the electronic circuit, a value of a signal for instructing the electronic circuit to perform resetting.

8. The control system according to claim 1, wherein the signal maintaining circuit is configured to maintain, as the signal to be output from the bus interface to the electronic circuit, a value of a signal for instructing on and off of power supply to the electronic circuit.

9. A relay apparatus comprising:

a relay circuit configured to relay signals transmitted and received between a plurality of information processing apparatuses;

a bus interface configured to receive, via a bus, a control signal for controlling the relay circuit, and output a signal corresponding to the received control signal to the relay circuit;

a signal maintaining circuit configured to maintain a value of the signal to be output from the bus interface to the relay circuit; and

a reset control circuit configured to cause the signal maintaining circuit to maintain the value of the output signal to the relay circuit, and subsequently reset the bus interface.

10. The relay apparatus according to claim 9, wherein the reset control circuit is configured to, upon receiving a reset instruction via a reset signal line from a control device connected to the bus, cause the signal maintaining circuit to maintain the value of the output signal to the relay circuit, and subsequently reset the bus interface.

11. The relay apparatus according to claim 10, wherein the bus interface is configured to, after being reset by the reset control circuit, output again to the signal maintaining circuit a value of a signal being output from the signal maintaining circuit to the relay circuit, in accordance with an instruction from the control device via the bus.

12. The relay apparatus according to claim 11, wherein the bus interface is configured to output again to the signal maintaining circuit the value of the signal being output from the signal maintaining circuit to the relay circuit, by loading the value of the signal being output from the signal maintaining circuit to the relay circuit and outputting the loaded value of the signal to the signal maintaining circuit.

13. The relay apparatus according to claim 11, wherein after the bus interface has output again to the signal maintaining circuit the value of the signal being output from the signal maintaining circuit to the relay circuit, the reset control circuit releases the signal maintaining circuit from a state of maintaining the value of the output signal to the relay circuit.

14. The relay apparatus according to claim 13,

wherein the bus interface is instructed by the control device via the bus to output again to the signal maintaining circuit the value of the signal being output from the signal maintaining circuit to the relay circuit, and subsequently receives from the control device via the bus a release instruction for releasing the signal maintaining circuit from the state of maintaining the value of the output signal;

and

wherein the reset control circuit is configured to, in response to reception of the release instruction by the bus interface, release the signal maintaining circuit from the state of maintaining the value of the output signal to the relay circuit.

15. The relay apparatus according to claim 10, wherein the signal maintaining circuit is configured to maintain, as the signal to be output from the bus interface to the relay circuit, a value of a signal for instructing the relay circuit to perform resetting.

16. The relay apparatus according to claim 10, wherein the signal maintaining circuit is configured to maintain, as the signal to be output from the bus interface to the relay circuit, a value of a signal for instructing on and off of power supply to the relay circuit.