VERIFYING DATA RECEIVED OUT-OF-ORDER FROM A BUS

• US 20130159591A1
• Filed: 12/14/2011
• Published: 06/20/2013
• Est. Priority Date: 12/14/2011
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hickey, Mark J., Ouda, Ibrahim A., Acua, Victor A., Lyle, Galen A.
• Application Number:
  US13/325,701
• Publication Number:
  US 20130159591A1
• Time in Patent Office: Days
• US Class Current: 710/310
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults

Abstract

In an embodiment, load transactions are issued to a bus. The load transactions are stalled if the bus cannot accept additional load transactions, and the load transactions are restarted after the bus can accept the additional load transactions. Responses are received from the bus to the load transactions out-of-order from an order that the load transactions were sent to the bus. The responses comprise data and index values that indicate an order that the load transactions were received by the bus. The data is compared in the order that the load transactions were received by the bus against expected data in the order that the load transaction were sent to the bus.

Claims

1. A method comprising:

issuing load transactions to a bus;

stalling the issuing the load transactions to the bus if the bus cannot accept additional load transactions and restarting the issuing after the bus can accept the additional load transactions;

receiving responses to the load transactions from the bus out-of-order from an order that the issuing sent the load transactions to the bus, wherein the responses comprise data and index values that indicate an order that the load transactions were received by the bus; and

comparing data in the responses in the order that the load transactions were received by the bus against expected data in the order that the load transaction were sent by the issuing.

2. The method of claim 1, wherein the stalling the issuing the load transactions to the bus if the bus cannot accept the additional load transactions further comprises:

incrementing a counter in response to the issuing the load transactions.

3. The method of claim 2, wherein the stalling the issuing the load transactions to the bus if the bus cannot accept the additional load transactions further comprises:

decrementing the counter in response to the receiving the responses to the load transactions.

4. The method of claim 3, wherein the stalling the issuing the load transactions to the bus if the bus cannot accept the additional load transactions further comprises:

stalling the issuing the transactions to the bus if the counter is greater than a maximum number of outstanding load transactions.

5. The method of claim 4, wherein the restarting the issuing after the bus can accept the additional load transactions further comprises:

restarting the issuing the transactions to the bus if the counter is less than the maximum number of outstanding load transactions.

6. The method of claim 1, further comprising:

creating a field programmable gate array image that performs the issuing, the stalling, the receiving, and the comparing; and

sending the field programmable gate array image to a field programmable gate array.

7. The method of claim 6, wherein the creating the field programmable gate array image further comprises:

creating parsed data from a bus transaction specification.

8. The method of claim 7, wherein the creating the field programmable gate array image further comprises:

generating randomized bus transactions from the parsed data.

9. The method of claim 8, wherein the creating the field programmable gate array image further comprises:

generating hardware description language code from the randomized bus transactions; and

imbedding functions into the hardware description language code to verify data integrity of the bus transactions.

10. A computer-readable storage medium encoded with instructions, wherein the instructions when executed comprise:

creating a field programmable gate array image; and

sending the field programmable gate array image to a field programmable gate array, wherein the field programmable gate array performs

issuing load transactions to a bus,

stalling the issuing the load transactions to the bus if the bus cannot accept additional load transactions and restarting the issuing after the bus can accept the additional load transactions,

receiving responses to the load transactions from the bus out-of-order from an order that the issuing sent the load transactions to the bus, wherein the responses comprise data and index values that indicate an order that the load transactions were received by the bus, and

comparing data in the responses in the order that the load transactions were received by the bus against expected data in the order that the load transaction were sent by the issuing.

11. The computer-readable storage medium of claim 10, wherein the stalling the issuing the load transactions to the bus if the bus cannot accept the additional load transactions further comprises:

incrementing a counter in response to the issuing the load transactions.

12. The computer-readable storage medium of claim 11, wherein the stalling the issuing the load transactions to the bus if the bus cannot accept the additional load transactions further comprises:

decrementing the counter in response to the receiving the responses to the load transactions.

13. The computer-readable storage medium of claim 12, wherein the stalling the issuing the load transactions to the bus if the bus cannot accept the additional load transactions further comprises:

stalling the issuing the transactions to the bus if the counter is greater than a maximum number of outstanding load transactions.

14. The computer-readable storage medium of claim 13, wherein the restarting the issuing after the bus can accept the additional load transactions further comprises:

restarting the issuing the transactions to the bus if the counter is less than the maximum number of outstanding load transactions.

15. The computer-readable storage medium of claim 10, wherein the creating the field programmable gate array image further comprises:

creating parsed data from a bus transaction specification;

generating randomized bus transactions from the parsed data;

generating hardware description language code from the randomized bus transactions; and

imbedding functions into the hardware description language code to verify data integrity of the bus transactions.

16. A computer comprising:

a processor;

a field programmable gate array comprising a field programmable gate array image; and

memory communicatively coupled to the processor and the field programmable gate array, wherein the memory is encoded with instructions, and wherein the instructions when executed by the processor comprise;

creating the field programmable gate array image, and

sending the field programmable gate array image to the field programmable gate array, wherein the field programmable gate array image causes the field programmable gate array to perform

issuing load transactions to a bus,

stalling the issuing the load transactions to the bus if the bus cannot accept additional load transactions and restarting the issuing after the bus can accept the additional load transactions,

receiving responses to the load transactions from the bus out-of-order from an order that the issuing sent the load transactions to the bus, wherein the responses comprise data and index values that indicate an order that the load transactions were received by the bus, and

comparing data in the responses in the order that the load transactions were received by the bus against expected data in the order that the load transaction were sent by the issuing.

17. The computer of claim 16, wherein the stalling the issuing the load transactions to the bus if the bus cannot accept the additional load transactions further comprises:

incrementing a counter in response to the issuing the load transactions; and

decrementing the counter in response to the receiving the responses to the load transactions.

18. The computer of claim 17, wherein the stalling the issuing the load transactions to the bus if the bus cannot accept the additional load transactions further comprises:

stalling the issuing the transactions to the bus if the counter is greater than a maximum number of outstanding load transactions.

19. The computer of claim 18, wherein the restarting the issuing after the bus can accept the additional load transactions further comprises:

restarting the issuing the transactions to the bus if the counter is less than the maximum number of outstanding load transactions.

20. The computer of claim 16, wherein the creating the field programmable gate array image further comprises:

creating parsed data from a bus transaction specification;

generating randomized bus transactions from the parsed data;

generating hardware description language code from the randomized bus transactions; and

imbedding functions into the hardware description language code to verify data integrity of the bus transactions.