SPECIALIZED VECTOR INSTRUCTION AND DATAPATH FOR MATRIX MULTIPLICATION

• US 20130159665A1
• Filed: 12/15/2011
• Published: 06/20/2013
• Est. Priority Date: 12/15/2011
• Status: Abandoned Application

• Current Assignee: VeriSilicon Holdings Co., Ltd. (Verisilicon Microelectronics (Shanghai) Co. Ltd.)
• Original Assignee: VeriSilicon Holdings Co., Ltd. (Verisilicon Microelectronics (Shanghai) Co. Ltd.)
• Inventors: Kashyap, Asheesh
• Application Number:
  US13/327,519
• Publication Number:
  US 20130159665A1
• Time in Patent Office: Days
• US Class Current: 712/3
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register

Abstract

A data processing element includes an input unit configured to provide instructions for scalar, vector and array processing, and a scalar processing unit configured to provide a scalar pipeline datapath for processing a scalar quantity. Additionally, the data processing element includes a vector processing unit coupled to the scalar processing unit and configured to provide a vector pipeline datapath employing a vector register for processing a one-dimensional vector quantity. The data processing element further includes an array processing unit coupled to the vector processing unit and configured to provide an array pipeline datapath employing a parallel processing structure for processing a two-dimensional vector quantity. A method of operating a data processing element and a MIMO receiver employing a data processing element are also provided.

Claims

1. A data processing element, comprising:

an input unit configured to provide instructions for scalar, vector and array processing;

a scalar processing unit configured to provide a scalar pipeline datapath for processing a scalar quantity;

a vector processing unit coupled to the scalar processing unit and configured to provide a vector pipeline datapath employing a vector register for processing a one-dimensional vector quantity; and

an array processing unit coupled to the vector processing unit and configured to provide an array pipeline datapath employing a parallel processing structure for processing a two-dimensional vector quantity.

2. The data processing element as recited in claim 1 wherein the parallel processing structure includes a two-dimensional vector register for processing the two-dimensional vector quantity.

3. The data processing element as recited in claim 2 wherein a one-dimensional vector quantity can be inserted separately and directly into the two-dimensional register on a row-wise or a column-wise basis.

4. The data processing element as recited in claim 2 wherein a one-dimensional vector quantity can be extracted separately and directly from the two-dimensional register on a row-wise or a column-wise basis.

5. The data processing element as recited in claim 1 wherein the parallel processing structure includes a parallel multiplying accumulator for processing the two-dimensional vector quantity.

6. The data processing element as recited in claim 5 wherein the parallel multiplying accumulator provides a resultant one-dimensional vector quantity.

7. The data processing element as recited in claim 6 wherein the resultant one-dimensional vector quantity is processed in the vector pipeline datapath.

8. A method of operating a data processing element, comprising:

fetching instructions for scalar, vector and array processing;

processing a scalar quantity through a scalar pipeline datapath;

also processing a one-dimensional vector quantity through a vector pipeline datapath employing a vector register; and

further processing a two-dimensional vector quantity through an array pipeline datapath employing a parallel processing structure.

9. The method as recited in claim 8 wherein the parallel processing structure includes a two-dimensional vector register for processing the two-dimensional vector quantity.

10. The method as recited in claim 9 wherein a one-dimensional vector quantity can be inserted separately and directly into the two-dimensional register on a row-wise or a column-wise basis.

11. The method as recited in claim 9 wherein a one-dimensional vector quantity can be extracted separately and directly from the two-dimensional register on a row-wise or a column-wise basis.

12. The method as recited in claim 8 wherein the parallel processing structure includes a parallel multiplying accumulator for processing the two-dimensional vector quantity.

13. The method as recited in claim 12 wherein the parallel multiplying accumulator provides a resultant one-dimensional vector quantity.

14. The method as recited in claim 13 wherein the resultant one-dimensional vector quantity is processed in the vector pipeline datapath.

15. a MIMO receiver, comprising:

a MIMO input element, coupled to multiple receive antennas, that provides receive data for scalar, vector and array processing;

a data processing element, including;

an input unit that provides instructions for the scalar, vector and array processing,

a scalar processing unit that provides a scalar pipeline datapath for processing scalar data,

a vector processing unit, coupled to the scalar processing unit, that provides a vector pipeline datapath employing a vector register for processing one-dimensional vector data, and

an array processing unit, coupled to the vector processing unit, that provides an array pipeline datapath having a parallel processing structure for processing two-dimensional vector data; and

a MIMO output element, coupled to the data processing element, that provides an output data stream corresponding to the receive data.

16. The receiver as recited in claim 15 wherein the parallel processing structure includes a two-dimensional vector register for processing the two-dimensional vector data.

17. The receiver as recited in claim 16 wherein one-dimensional vector data can be inserted separately and directly into the two-dimensional register on a row-wise or a column-wise basis.

18. The receiver as recited in claim 16 wherein one-dimensional vector data can be extracted separately and directly from the two-dimensional register on a row-wise or a column-wise basis.

19. The receiver as recited in claim 15 wherein the parallel processing structure includes a parallel multiplying accumulator for processing the two-dimensional vector data.

20. The receiver as recited in claim 19 wherein the parallel multiplying accumulator provides resultant one-dimensional vector data.