MEMORY ARCHITECTURE FOR READ-MODIFY-WRITE OPERATIONS

• US 20130159812A1
• Filed: 12/16/2011
• Published: 06/20/2013
• Est. Priority Date: 12/16/2011
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: LOH, Gabriel H., O'Connor, James M., Ignatowski, Michael, Jayasena, Nuwan S., Beckmann, Bradford M.
• Application Number:
  US13/328,393
• Publication Number:
  US 20130159812A1
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array

Abstract

According to one embodiment, a memory architecture implemented method is provided, where the memory architecture includes a logic chip and one or more memory chips on a single die, and where the method comprises: reading values of data from the one or more memory chips to the logic chip, where the one or more memory chips and the logic chip are on a single die; modifying, via the logic chip on the single die, the values of data; and writing, from the logic chip to the one or more memory chips, the modified values of data.

Claims

1. A memory architecture implemented method, where the memory architecture includes a logic chip and one or more memory chips on a single die and where the method comprises:

reading values of data from the one or more memory chips to the logic chip, where the one or more memory chips and the logic chip are on a single die;

modifying, via the logic chip on the single die, the values of data; and

writing, from the logic chip to at least one of the one or more memory chips, the modified values of data.

2. The memory architecture implemented method of claim 1, further comprising:

receiving a modify command from an external client, where the modify command instructs the logic chip regarding modifying the values of data, and where the external client is not on the single die with the one or more memory chips and the logic chip.

3. The memory architecture implemented method of claim 2, further comprising:

sending a completion code to the external client, where the completion code is sent by the logic chip in response to completion of instructions contained in the modify command.

4. The memory architecture implemented method of claim 3, where:

the modify command includes an atomic increment command, and where;

reading values of data includes reading the values of data from a specified address,

modifying the values of data includes modifying the values of data by incrementing the values by an increment amount specified by the atomic increment command,

writing the modified values of data includes writing the incremented values, and

sending the completion code includes sending an atomic increment completion code to the external client.

5. The memory architecture implemented method of claim 1, where the values of data comprise error correction code protected data, and where:

modifying the values of data includes modifying the values of data and computing new error correcting code parity bits, and

writing the modified values of data includes writing the modified values of data and the new error correcting code parity bits to at least one of the one or more memory chips.

6. The memory architecture implemented method of claim 1, where the method is initiated using a single compound command, a sequence of commands, or a combination of single and sequence commands.

7. The memory architecture implemented method of claim 1, further comprising:

searching, by the logic chip, in memory of at least one of the one or more memory chips for values of data,

comparing, by the logic chip, values of data in at least one of the one or more memory chips,

searching, by the logic chip, values of data in at least one of the one or more memory chips to find a minimum and/or maximum value, or

summing, by the logic chip, a set of the values of data in at least one of the one or more memory chips.

8. A stacked memory architecture implemented on a single die, the stacked memory architecture comprising:

one or more memory layers; and

a logic layer, where the logic layer is vertically stacked with the one or more memory layers, and where the logic layer includes logic instructions to perform a read-modify-write operation within the single die.

9. The stacked memory architecture of claim 8, where the logic layer is to execute the logic instructions to:

read, from at least one of the one or more memory layers, values of data;

modify, via the logic layer, the values of data;

write, from the logic layer to at least one of the one or more memory layers, the modified values of data.

10. The stacked memory architecture of claim 9, where the logic layer is to execute the logic instructions to further:

receive a modify command from an external client, where the external client is not on the single die with the one or more memory chips and the logic chip, and where the modify command instructs the logic layer regarding the modifying of the values of data, and/or

send a completion code to the external client, where the external client is not on the single die with the one or more memory chips and the logic chip, and where the completion code is sent by the logic layer in response to completion of instructions contained in the modify command from the external client.

11. The stacked memory architecture of claim 10, where the logic layer is to execute the logic instructions from the modify command from the external client, where the modify command is an atomic increment command, and where logic layer is to execute the logic instruction to:

modify the values of data by an atomic increment amount, and

send an atomic increment completion code to the external client.

12. The stacked memory architecture of claim 9, where the stacked memory architecture comprises error correction code memory, and where the logic layer is to execute logic instructions to:

modify the values of data and compute new error correcting code parity bits, and

write the modified data and new error correcting code parity bits to at least one of the one or more memory layers.

13. The stacked memory architecture of claim 8, where the logic layer is to execute logic instructions to further:

search, by the logic layer, in memory of at least one of the one or more memory layers for values of data,

compare, by the logic layer, the values of data in at least one of the one or more memory layers,

search, by the logic layer, the values of data in at least one of the one or more memory layers to find a minimum and/or maximum value, or

sum, by the logic layer, the values of data in at least one of the one or more memory layers.

14. A side-split memory architecture implemented on a single die, the side-split memory architecture comprising:

one or more memory layers; and

a logic layer, where the logic layer is horizontally separated from the one or more memory layers, and where the logic layer includes logic instructions to perform a read-modify-write operation within the single die.

15. The side-split memory architecture of claim 14, where the logic layer is to execute the logic instructions to:

read, from at least one of the one or more memory layers, values of data;

modify, via the logic layer, the values of data;

write, from the logic layer to at least one of the one or more memory layers, the modified values of data.

16. The side-split memory architecture of claim 15, where the logic layer is to execute the logic instructions to further:

receive a modify command from an external client, where the external client is not on the single die with the one or more memory chips and the logic chip, and where the modify command instructs the logic layer regarding the modifying of the values of data, and/or

send a completion code to the external client, where the external client is not on the single die with the one or more memory chips and the logic chip, and where the completion code is sent by the logic layer in response to completion of instructions contained in the modify command from the external client.

17. The side-split memory architecture of claim 16, where the logic layer is to execute the logic instructions from the modify command from the external client, where the modify command is an atomic increment command, and where logic layer is to execute the logic instruction to:

modify the values of data by an atomic increment amount, and

send an atomic increment completion code to the external client.

18. The side-split memory architecture of claim 15, where the stacked memory architecture comprises error correction code memory, and where the logic layer is to execute logic instructions to:

modify the values of data and compute new error correcting code parity bits, and

write the modified data and new error correcting code parity bits to at least one of the one or more memory layers.

19. The side-split memory architecture of claim 14, where the logic layer is to execute logic instructions to further:

search, by the logic layer, in memory of at least one of the one or more memory layers for values of data,

compare, by the logic layer, the values of data in at least one of the one or more memory layers,

search, by the logic layer, the values of data in at least one of the one or more memory layers to find a minimum and/or maximum value, or

sum, by the logic layer, the values of data in at least one of the one or more memory layers.

20. An error correcting code memory, comprising:

one or more memory chips formed on a die; and

a logic chip formed on the die with the one or more memory chips, where the logic chip is to perform at least one of a first operation or a second operation, where the logic chip, when performing the first operation, is to;

read error correction code protected data from at least one of the one or more memory chips,

modify the error correcting code protected data,

compute new error correcting code parity bits associated with the error correcting code protected data, and

write the modified error correcting code protected data and the new error correcting code parity bits to at least one of the one or more memory chips; and

where the logic chip, when performing the second operation, is to;

read error correction code protected data from at least one of the one or more memory chips,

determine whether an error is detected,

modify the data and/or error correcting code parity bits when an error is detected, and

write the modified data and/or error correcting code parity bits to at least one of the one or more memory chips.