READING CIRCUIT OF GYROSCOPE

• US 20130160544A1
• Filed: 03/26/2012
• Published: 06/27/2013
• Est. Priority Date: 12/26/2011
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Hsu, Yu-Wen, Liao, Lu-Po, Chiu, Sheng-Ren, Lin, Shih-Ting
• Granted Patent: US 8,857,259 B2
• Time in Patent Office: Days
• US Class Current: 73/504.12
• CPC Class Codes: G01C 19/5776 Signal processing not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719

Abstract

A reading circuit of a gyroscope is provided. The reading circuit includes a driving unit, a high pass filter, a signal processing unit, and a low pass filter. The driving unit generates a resonance signal for a resonator of the gyroscope and generates a demodulation signal for the signal processing unit. The signal processing unit provides a modulation signal to a Coriolis accelerometer of the gyroscope. An input terminal of the high pass filter receives an output signal of the Coriolis accelerometer. The signal processing unit processes and demodulates an output of the high pass filter according to the demodulation signal and outputs a demodulation result to the low pass filter.

Claims

1. A reading circuit of a gyroscope, comprising:

a driving unit, generating a resonance signal for a resonator of the gyroscope, and generating a demodulation signal;

a high pass filter, having an input terminal for receiving an output signal of a Coriolis accelerometer of the gyroscope;

a signal processing unit, coupled to the driving unit and the high pass filter, providing a modulation signal to the Coriolis accelerometer, and processing and demodulating an output of the high pass filter according to the demodulation signal to output a demodulation result; and

a low pass filter, coupled to the signal processing unit and receiving the demodulation result.

2. The reading circuit according to claim 1, wherein the resonance signal and the demodulation signal have a same frequency, and the resonance signal and the demodulation signal have different phases.

3. The reading circuit according to claim 1, wherein a frequency of the modulation signal is greater than a frequency of the resonance signal.

4. The reading circuit according to claim 1 further comprising:

a bias resistor, wherein a first end of the bias resistor is coupled to the input terminal of the high pass filter, and a second end of the bias resistor is coupled to a reference voltage.

5. The reading circuit according to claim 1, wherein the high pass filter comprises:

a capacitor, wherein a first end of the capacitor is served as the input terminal of the high pass filter, and a second end of the capacitor is served as an output terminal of the high pass filter.

6. The reading circuit according to claim 1, wherein the low pass filter comprises:

a resistor, wherein a first end of the resistor is served as an input terminal of the low pass filter, and a second end of the resistor is served as an output terminal of the low pass filter; and

a capacitor, wherein a first end of the capacitor is coupled to the second end of the resistor, and a second end of the capacitor is coupled to a reference voltage.

7. The reading circuit according to claim 1, wherein the driving unit comprises:

an amplifier, having a first input terminal and a second input terminal respectively coupled to a first sensing terminal and a second sensing terminal of the resonator, wherein a first output terminal and a second output terminal of the amplifier respectively coupled to a first driving terminal and a second driving terminal of the resonator for providing the resonance signal; and

a phase locked loop (PLL), having a first input terminal and a second input terminal respectively coupled to the first output terminal and the second output terminal of the amplifier, wherein an output terminal of the PLL provides the demodulation signal to the signal processing unit.

8. The reading circuit according to claim 1, wherein the signal processing unit comprises:

an integrator, having an input terminal coupled to an output terminal of the high pass filter;

a comparator, having an input terminal coupled to an output terminal of the integrator, and comparing an output of the integrator with a threshold;

a latch, having an input terminal coupled to an output terminal of the comparator, and latching an output of the comparator according to a clock signal;

a demodulator, having a first input terminal coupled to an output terminal of the latch, a second input terminal coupled to the driving unit for receiving the demodulation signal, and an output terminal for outputting the demodulation result; and

a modulation signal generator, coupled to the Coriolis accelerometer for providing the modulation signal.

9. The reading circuit according to claim 8, wherein the modulation signal generator comprises:

a first voltage source, providing a first reference voltage;

a second voltage source, providing a second reference voltage; and

a switch, having a first selection terminal coupled to the first voltage source, a second selection terminal coupled to the second voltage source, and a common terminal coupled to the Coriolis accelerometer, wherein the switch outputs the first reference voltage or the second reference voltage to the Coriolis accelerometer as the modulation signal according to an output of the latch.

10. The reading circuit according to claim 1, wherein the signal processing unit comprises:

an integrator, having an input terminal coupled to an output terminal of the high pass filter;

a quantizer, having an input terminal coupled to an output terminal of the integrator, and quantizing an output of the integrator;

a demodulator, having a first input terminal coupled to an output terminal of the quantizer, a second input terminal coupled to the driving unit for receiving the demodulation signal, and an output terminal for outputting the demodulation result; and

a modulation signal generator, coupled to the Coriolis accelerometer for providing the modulation signal.

11. The reading circuit according to claim 10, wherein the modulation signal generator comprises:

a voltage source, providing a first reference voltage, a second reference voltage, a third reference voltage, and a fourth reference voltage;

a first switch, having a first selection terminal for receiving the first reference voltage, a second selection terminal for receiving the second reference voltage, and a common terminal coupled to a first carrier input terminal of the Coriolis accelerometer, wherein the first switch outputs the first reference voltage or the second reference voltage to the first carrier input terminal of the Coriolis accelerometer according to an output of the quantizer; and

a second switch, having a first selection terminal for receiving the third reference voltage, a second selection terminal for receiving the fourth reference voltage, and a common terminal coupled to a second carrier input terminal of the Coriolis accelerometer, wherein the second switch outputs the third reference voltage or the fourth reference voltage to the second carrier input terminal of the Coriolis accelerometer according to the output of the quantizer.

12. The reading circuit according to claim 10, wherein the integrator comprises:

an amplifier, having a first input terminal served as the input terminal of the integrator;

a first capacitor, having a first end coupled to a common mode voltage, and a second end coupled to a second input terminal of the amplifier;

a second capacitor, having a first end coupled to the first input terminal of the amplifier;

a third capacitor, having a first end coupled to the second input terminal of the amplifier, wherein second ends of the second capacitor and the third capacitor are served as the output terminal of the integrator;

a first switch, having a first end coupled to the first end of the second capacitor, and a second end coupled to a first output terminal of the amplifier;

a second switch, having a first end coupled to the second end of the second capacitor, and a second end coupled to the first output terminal of the amplifier;

a third switch, having a first end coupled to the first end of the third capacitor, and a second end coupled to a second output terminal of the amplifier; and

a fourth switch, having a first end coupled to the second end of the third capacitor, and a second end coupled to the second output terminal of the amplifier.

13. The reading circuit according to claim 1, wherein the signal processing unit comprises:

an amplifier, having an input terminal coupled to an output terminal of the high pass filter;

a high frequency demodulator, having a first input terminal and a second input terminal respectively coupled to a first output terminal and a second output terminal of the amplifier;

a resonator demodulator, having a first input terminal and a second input terminal respectively coupled to a first output terminal and a second output terminal of the high frequency demodulator, and the resonator demodulator receiving the demodulation signal and demodulating an output of the high frequency demodulator according to the demodulation signal to provide the demodulation result to the low pass filter; and

a modulation signal generator, coupled to the Coriolis accelerometer and providing the modulation signal.

14. The reading circuit according to claim 13, wherein the signal processing unit further comprises:

a bias resistor, having a first end coupled to the input terminal of the amplifier and a second end coupled to a reference voltage.

15. The reading circuit according to claim 13, wherein the modulation signal generator comprises:

a first voltage source, providing a first reference voltage;

a second voltage source, providing a second reference voltage;

a first switch, having a first selection terminal for receiving the first reference voltage, a second selection terminal for receiving the second reference voltage, and a common terminal coupled to a first carrier input terminal of the Coriolis accelerometer, wherein the first switch outputs the first reference voltage or the second reference voltage to the first carrier input terminal of the Coriolis accelerometer according to a clock signal; and

a second switch, having a first selection terminal for receiving the first reference voltage, a second selection terminal for receiving the second reference voltage, and a common terminal coupled to a second carrier input terminal of the Coriolis accelerometer, wherein the second switch outputs the first reference voltage or the second reference voltage to the second carrier input terminal of the Coriolis accelerometer according to the clock signal.

16. The reading circuit according to claim 13, wherein the high frequency demodulator comprises:

a first switch, having a first end coupled to the first output terminal of the amplifier, and a second end coupled to the first input terminal of the resonator demodulator;

a second switch, having a first end coupled to the second output terminal of the amplifier, and a second end coupled to the second input terminal of the resonator demodulator;

a third switch, having a first end coupled to the first output terminal of the amplifier, and a second end coupled to the second input terminal of the resonator demodulator; and

a fourth switch, having a first end coupled to the second output terminal of the amplifier, and a second end coupled to the first input terminal of the resonator demodulator.

17. The reading circuit according to claim 13, wherein the resonator demodulator comprises:

a first resistor, having a first end coupled to a first voltage;

a second resistor, having a first end coupled to the first voltage;

a first transistor, having a first terminal coupled to a second end of the first resistor, and a control terminal for receiving a first terminal signal of the demodulation signal;

a second transistor, having a first terminal coupled to a second end of the second resistor, a second terminal coupled to a second terminal of the first transistor, and a control terminal for receiving a second terminal signal of the demodulation signal;

a third transistor, having a first terminal coupled to the second end of the first resistor, and a control terminal for receiving the second terminal signal of the demodulation signal;

a fourth transistor, having a first terminal coupled to the second end of the second resistor, a second terminal coupled to a second terminal of the third transistor, and a control terminal for receiving the first terminal signal of the demodulation signal;

a fifth transistor, having a first terminal coupled to the second terminals of the first transistor and the second transistor, and a control terminal coupled to the first output terminal of the high frequency demodulator;

a sixth transistor, having a first terminal coupled to the second terminals of the third transistor and the fourth transistor, a second terminal coupled to a second terminal of the fifth transistor, and a control terminal coupled to the second output terminal of the high frequency demodulator; and

a seventh transistor, having a first terminal coupled to the second terminals of the fifth transistor and the sixth transistor, a second terminal coupled to a reference voltage, and a control terminal coupled to a bias voltage.