SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20130161621A1
• Filed: 12/17/2012
• Published: 06/27/2013
• Est. Priority Date: 12/23/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: ISOBE, Atsuo, OKAZAKI, Yutaka, HANAOKA, Kazuya, SASAGAWA, Shinya, KURATA, Motomu
• Granted Patent: US 8,748,241 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.

Claims

1. A semiconductor device comprising:

an oxide semiconductor film over an insulating surface;

a gate insulating film over the oxide semiconductor film;

a gate electrode provided over the gate insulating film and overlapping with the oxide semiconductor film;

a first insulating film over the gate insulating film and the gate electrode;

a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film;

a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film; and

a second insulating film over the source electrode and the drain electrode,

wherein heights of top surfaces of the source electrode and the drain electrode are substantially the same as heights of top surfaces of the first insulating film and the second insulating film, and

wherein a channel length of the oxide semiconductor film is greater than or equal to 1 nm and less than or equal to 30 nm.

2. The semiconductor device according to claim 1,

wherein a distance between the gate electrode and a contact region in which the oxide semiconductor film is in contact with the source electrode is greater than or equal to 1 nm and less than or equal to 30 nm.

3. The semiconductor device according to claim 1,

wherein the semiconductor device further comprises a transistor including a semiconductor material having a band gap which is different from a band gap of the oxide semiconductor film.

4. The semiconductor device according to claim 1,

wherein the semiconductor device is a memory cell.

5. A semiconductor device comprising:

an oxide semiconductor film provided over an insulating surface and including a channel formation region, and a first low-resistance region and a second low-resistance region with the channel formation region sandwiched therebetween;

a gate insulating film over the oxide semiconductor film;

a gate electrode provided over the gate insulating film and overlapping with the channel formation region;

a first insulating film over the gate insulating film and the gate electrode;

a source electrode in contact with a part of the first low-resistance region;

a drain electrode in contact with a part of the second low-resistance region; and

a second insulating film over the source electrode and the drain electrode,

wherein heights of top surfaces of the source electrode and the drain electrode are substantially the same as heights of top surfaces of the first insulating film and the second insulating film, and

wherein a channel length of the oxide semiconductor film is greater than or equal to 1 nm and less than or equal to 30 nm.

6. The semiconductor device according to claim 5,

wherein a distance between the gate electrode and a contact region in which the oxide semiconductor film is in contact with the source electrode is greater than or equal to 1 nm and less than or equal to 30 nm.

7. The semiconductor device according to claim 5,

wherein the semiconductor device further comprises a transistor including a semiconductor material having a band gap which is different from a band gap of the oxide semiconductor film.

8. The semiconductor device according to claim 5,

wherein the semiconductor device is a memory cell.

9. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor film over an insulating surface;

forming a gate insulating film covering the oxide semiconductor film;

forming a first conductive film provided over the gate insulating film and overlapping with the oxide semiconductor film;

forming a film over the first conductive film;

forming a first resist by performing electron beam exposure over the film;

selectively etching the film using the first resist as a mask to form a hard mask film;

forming a gate electrode by selectively etching the first conductive film using the hard mask film as a mask;

forming a first insulating film over the gate insulating film and the gate electrode;

performing first removing treatment on a part of the first insulating film while the gate electrode is not exposed;

forming an anti-reflective film over the first insulating film subjected to the first removing treatment;

forming a second resist by performing electron beam exposure over the anti-reflective film and overlapping with the oxide semiconductor film;

exposing parts of the insulating surface and the oxide semiconductor film to form an exposed insulating surface and oxide semiconductor film by selectively etching the anti-reflective film, the first insulating film, and the gate insulating film;

forming a second conductive film over the exposed insulating surface and oxide semiconductor film, and the anti-reflective film;

forming a second insulating film over the second conductive film;

performing second removing treatment on parts of the second insulating film and the second conductive film, and the anti-reflective film so that the first insulating film is exposed; and

forming a source electrode and a drain electrode by processing the second conductive film subjected to the second removing treatment.

10. The method for manufacturing the semiconductor device, according to claim 9, wherein the first removing treatment is performed by chemical mechanical polishing.

11. The method for manufacturing the semiconductor device, according to claim 9, wherein the second removing treatment is performed by chemical mechanical polishing.

12. The method for manufacturing the semiconductor device, according to claim 9,

wherein the film is a stacked film of a silicon nitride oxide film and an amorphous silicon film or a stacked film of a silicon oxide film and an amorphous silicon film, and

wherein the amorphous silicon film is formed over the silicon nitride oxide film or the silicon oxide film.

13. The method for manufacturing a semiconductor device, according to claim 9,

wherein a second hard mask film is formed after the anti-reflective film is formed and before the second resist is formed, and

wherein the second hard mask film is a stacked film of a silicon nitride oxide film and an amorphous silicon film or a stacked film of a silicon oxide film and an amorphous silicon film.

14. The method for manufacturing a semiconductor device, according to claim 9, wherein a channel length of the oxide semiconductor film is determined by electron beam exposure.

15. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor film over an insulating surface;

forming a gate insulating film covering the oxide semiconductor film;

forming a first conductive film provided over the gate insulating film and overlapping with the oxide semiconductor film;

forming a film over the first conductive film;

forming a first resist by performing electron beam exposure over the film;

selectively etching the film using the first resist as a mask to form a hard mask film;

forming a gate electrode by selectively etching the first conductive film using the hard mask film as a mask;

forming, in a self-aligned manner, a channel formation region in a region overlapping with the gate electrode in the oxide semiconductor film and a first low-resistance region and a second low-resistance region between which the channel formation region is sandwiched in the oxide semiconductor film by adding impurities;

forming a first insulating film over the gate insulating film and the gate electrode;

performing first removing treatment on a part of the first insulating film while the gate electrode is not exposed;

forming an anti-reflective film over the first insulating film on which the first removing treatment is performed;

forming a second resist by performing electron beam exposure over the anti-reflective film and overlapping with the channel formation region, the first low-resistance region, and the second low-resistance region;

exposing a part of the insulating surface, the first low-resistance region, and the second low-resistance region by selectively etching the anti-reflective film, the first insulating film, and the gate insulating film to form an exposed insulating surface, first low-resistance region, and second low-resistance region;

forming a second conductive film over the exposed insulating surface, first low-resistance region, and second low-resistance region, and the anti-reflective film;

forming a second insulating film over the second conductive film;

performing second removing treatment on parts of the second insulating film and the second conductive film, and the anti-reflective film so that the first insulating film is exposed; and

forming a source electrode and a drain electrode by processing the second conductive film on which the second removing treatment is performed.

16. The method for manufacturing the semiconductor device, according to claim 15, wherein the first removing treatment is performed by chemical mechanical polishing.

17. The method for manufacturing the semiconductor device, according to claim 15, wherein the second removing treatment is performed by chemical mechanical polishing.

18. The method for manufacturing the semiconductor device, according to claim 15,

wherein the film is a stacked film of a silicon nitride oxide film and an amorphous silicon film or a stacked film of a silicon oxide film and an amorphous silicon film, and

wherein the amorphous silicon film is formed over the silicon nitride oxide film or the silicon oxide film.

19. The method for manufacturing a semiconductor device, according to claim 15,

wherein a second hard mask film is formed after the anti-reflective film is formed and before the second resist is formed, and

wherein the second hard mask film is a stacked film of a silicon nitride oxide film and an amorphous silicon film or a stacked film of a silicon oxide film and an amorphous silicon film.

20. The method for manufacturing a semiconductor device, according to claim 15, wherein a channel length of the channel formation region is determined by electron beam exposure.

21. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor film over an insulating surface;

forming a gate insulating film covering the oxide semiconductor film;

forming a first conductive film provided over the gate insulating film and overlapping with the oxide semiconductor film;

forming a film over the first conductive film;

forming a first resist by performing electron beam exposure over the film;

selectively etching the film using the first resist as a mask to form a hard mask film;

forming a gate electrode by selectively etching the first conductive film using the hard mask film as a mask;

forming a first insulating film over the gate insulating film and the gate electrode;

performing first removing treatment on a part of the first insulating film while the gate electrode is not exposed;

forming an anti-reflective film over the first insulating film subjected to the first removing treatment;

forming a second resist by performing electron beam exposure over the anti-reflective film and overlapping with the oxide semiconductor film;

exposing parts of the insulating surface and the oxide semiconductor film to form an exposed insulating surface and oxide semiconductor film by selectively etching the anti-reflective film, the first insulating film, and the gate insulating film;

forming a second conductive film over the exposed insulating surface and oxide semiconductor film, and the anti-reflective film;

forming a second insulating film over the second conductive film; and

performing second removing treatment on parts of the second insulating film and the second conductive film, and the anti-reflective film so that the first insulating film is exposed.

22. The method for manufacturing the semiconductor device, according to claim 21, wherein the first removing treatment is performed by chemical mechanical polishing.

23. The method for manufacturing the semiconductor device, according to claim 21, wherein the second removing treatment is performed by chemical mechanical polishing.

24. The method for manufacturing the semiconductor device, according to claim 21,

wherein the film is a stacked film of a silicon nitride oxide film and an amorphous silicon film or a stacked film of a silicon oxide film and an amorphous silicon film, and

wherein the amorphous silicon film is formed over the silicon nitride oxide film or the silicon oxide film.

25. The method for manufacturing a semiconductor device, according to claim 21,

wherein a second hard mask film is formed after the anti-reflective film is formed before the second resist is formed, and

wherein the second hard mask film is a stacked film of a silicon nitride oxide film and an amorphous silicon film or a stacked film of a silicon oxide film and an amorphous silicon film.

26. The method for manufacturing a semiconductor device, according to claim 21, wherein a channel length of the oxide semiconductor film is determined by electron beam exposure.

27. The method for manufacturing the semiconductor device, according to claim 21, wherein a source electrode and a drain electrode are formed by performing the second removing treatment.