E-MODE HFET DEVICE

• US 20130161698A1
• Filed: 12/27/2011
• Published: 06/27/2013
• Est. Priority Date: 12/27/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Fabio Alessio Marino, Paolo Menegoli
• Inventors: Marino, Fabio Alessio, Menegoli, Paolo
• Granted Patent: US 8,669,591 B2
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/1075 of field-effect transistors
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/7782 with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

The present invention describes a transistor based on a Hetero junction FET structure, where the metal gate has been replaced by a stack formed by a highly doped compound semiconductor and an insulating layer in order to achieve enhancement mode operation and at the same time drastically reduce the gate current leakage. The combination of the insulating layer with a highly doped semiconductor allows the tuning of the threshold voltage of the device at the desired value by simply changing the composition of the semiconductor layer forming the gate region and/or its doping allowing a higher degree of freedom. In one of the embodiment, a back-barrier layer and a heavily doped threshold tuning layer are used to suppress Short Channel Effect phenomena and to adjust the threshold voltage of the device at the desired value. The present invention can be realized both with polar and non-polar (or semi-polar) materials.

Claims

1. A semiconductor field effect transistor comprising:

at least one compound semiconductor layer, formed with at least one of the semiconductor materials belonging to the group comprising III-V and II-VI compounds semiconductors;

at least one insulating layer formed above at least a portion of at least one of said compound semiconductor layers;

at least one semiconductor gate region formed above at least a portion of at least one of said insulating layers;

a source and a drain region;

wherein at least one of said semiconductor gate regions is heavily doped.

2. The semiconductor field effect transistor of claim 1, further comprising a carrier transport layer;

wherein at least one of said compound semiconductor layers is a barrier layer;

wherein said barrier layer is formed above at least a portion of said carrier transport layer, and whereby the conductive channel of said semiconductor field effect transistor is formed in said carrier transport layer when said semiconductor field effect transistor is turned on.

3. The semiconductor field effect transistor of claim 1, wherein at least one of said compound semiconductor layers is a carrier transport layer, and

whereby the conductive channel of said semiconductor field effect transistor is formed in said carrier transport layer when said semiconductor field effect transistor is turned on.

4. The semiconductor field effect transistor of claim 1, wherein at least one of said semiconductor gate regions is formed with at least one of the semiconductor materials belonging to the group comprising III-V and II-VI compounds semiconductors.

5. The semiconductor field effect transistor of claim 1, further comprising at least one back-barrier layer;

wherein at least one of said compound semiconductor layers is a carrier transport layer;

wherein said back-barrier layer is formed under said carrier transport layer, and

whereby the conductive channel of said semiconductor field effect transistor is formed in said carrier transport layer when said semiconductor field effect transistor is turned on.

6. The semiconductor field effect transistor of claim 1, further comprising at least one heavily doped threshold voltage tuning layer.

7. The semiconductor field effect transistor of claim 1, wherein at least one of said source and drain regions is self-aligned with at least one of said semiconductor gate regions.

8. The semiconductor field effect transistor of claim 1, further comprising at least one lightly doped region self-aligned with at least one of said gate regions;

wherein at least one of said source and drain regions is self-aligned with at least one of said lightly doped regions.

9. The semiconductor field effect transistor of claim 1 in N-face configuration, further comprising at least one compound barrier layer under at least one of said compound semiconductor layers;

whereby at least one of the conductive channels of said semiconductor field effect transistor is formed at the upper interface of said compound barrier layer and said compound semiconductor layer when said semiconductor field effect transistor is turned on.

10. The semiconductor field effect transistor of claim 1 in N-face configuration, further comprising

a carrier transport layer;

at least one compound barrier layer under said carrier transport layer;

wherein at least one of said compound semiconductor layers is a threshold tuning layer;

wherein said threshold tuning layer is formed above at least a portion of said carrier transport layer, and

whereby at least one of the conductive channels of said semiconductor field effect transistor is formed at the upper interface of said compound barrier layer and said compound semiconductor layer when said semiconductor field effect transistor is turned on.

11. The semiconductor field effect transistor of claim 1, further comprising two barrier regions separated one from each other so that at least one of said gate regions can be formed between said two barrier regions;

wherein said two barrier regions are formed above at least a portion of at least one of said compound semiconductor layers.

12. The semiconductor field effect transistor of claim 1, further comprising a carrier transport layer;

at least one highly doped region above at least a portion of at least one of said compound semiconductor layers;

wherein at least one of said compound semiconductor layers is a barrier layer;

wherein said barrier layer is formed above at least a portion of said carrier transport layer, and

whereby the presence of said highly doped regions decreases the access resistance of said semiconductor field effect transistor.

13. A method for manufacturing a semiconductor field effect transistor comprising:

forming at least one compound semiconductor layer, with at least one of the semiconductor materials belonging to the group comprising III-V and II-VI compounds semiconductors;

forming at least one insulating layer above at least a portion of at least one of said compound semiconductor layers, by means of deposition or thermal growth process steps;

forming at least one semiconductor gate region above at least a portion of at least one of said insulating layers, by means of deposition and etching process steps, and

forming a source and a drain region;

wherein at least one of said semiconductor gate regions is heavily doped.

14. The method of claim 13, wherein said semiconductor field effect transistor comprises at least one back-barrier layer;

wherein at least one of said compound semiconductor layers is a carrier transport layer;

wherein said back-barrier layer is formed under said carrier transport layer, and

whereby the conductive channel of said semiconductor field effect transistor is formed in said carrier transport layer when said semiconductor field effect transistor is turned on.

15. The method of claim 13, wherein said semiconductor field effect transistor comprises at least one heavily doped threshold voltage tuning layer.

16. The method of claim 13, wherein at least one of said source and drain regions is formed self-aligned with at least one of said semiconductor gate regions.

17. The method of claim 13, further comprising forming at least one compound barrier layer under at least one of said compound semiconductor layers;

wherein said semiconductor field effect transistor has a N-face configuration, and

whereby at least one of the conductive channels of said semiconductor field effect transistor is formed at the interface between at least one of said compound barrier layers and at least one of said compound semiconductor layers when said semiconductor field effect transistor is turned on.

18. A semiconductor field effect transistor comprising:

at least one compound semiconductor layer, formed with at least one of the semiconductor materials belonging to the group comprising III-V and II-VI compounds semiconductors;

at least one gate region;

a source and a drain region, and

at least one heavily doped threshold voltage tuning layer.

19. The semiconductor field effect transistor of claim 18, further comprising at least one back-barrier layer;

wherein at least one of said compound semiconductor layers is a carrier transport layer;

wherein said back-barrier layer is formed under said carrier transport layer, and

whereby the conductive channel of said semiconductor field effect transistor is formed in said carrier transport layer when said semiconductor field effect transistor is turned on.

20. The semiconductor field effect transistor of claim 18, wherein at least one of said source and drain regions is self-aligned with at least one of said semiconductor gate regions.

21. The semiconductor field effect transistor of claim 18, further comprising at least an insulating layer between said compound semiconductor layer and said gate region, wherein said gate region is a highly conductive region.

22. The semiconductor field effect transistor of claim 18 in N-face configuration, further comprising at least one compound barrier layer under at least one of said compound semiconductor layers;

whereby at least one of the conductive channels of said semiconductor field effect transistor is formed at the interface between at least one of said compound barrier layers and at least one of said compound semiconductor layers when said semiconductor field effect transistor is turned on.