SEMICONDUCTOR MEMORY DEVICE

• US 20130161713A1
• Filed: 12/18/2012
• Published: 06/27/2013
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun
• Granted Patent: US 8,907,392 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/036 the capacitor extending under the transistor
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A semiconductor memory device which includes a memory cell including two or more sub memory cells is provided. The sub memory cells each including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In the semiconductor device, the sub memory cells are stacked in the memory cell; a first gate and a second gate are formed with a semiconductor film provided therebetween in the transistor; the first gate and the second gate are connected to the word line; one of a source and a drain of the transistor is connected to the bit line; the other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor; and the first gate and the second gate of the transistor in each sub memory cell overlap with each other and are connected to each other.

Claims

1. A semiconductor memory device comprising a memory cell including two or more sub memory cells, the sub memory cells each including:

a word line;

a bit line;

a first capacitor;

a second capacitor; and

a transistor,

wherein the sub memory cells are stacked in the memory cell,

wherein the transistor comprises a first gate, a second gate and a semiconductor film between the first gate and the second gate,

wherein the first gate and the second gate are electrically connected to the word line,

wherein one of a source and a drain of the transistor is electrically connected to the bit line,

wherein the other of the source and the drain of the transistor is electrically connected to the first capacitor and the second capacitor, and

wherein the first gate and the second gate of the transistor overlap with each other and are electrically connected to each other.

2. The semiconductor memory device according to claim 1, wherein the first capacitor and the second capacitor overlap with each other.

3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device includes a plurality of memory cells formed in matrix in a plane.

4. The semiconductor memory device according to claim 1, wherein the semiconductor film includes an oxide semiconductor.

5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device further comprises a transistor including silicon and overlapping with the sub memory cells.

6. The semiconductor memory device according to claim 1, wherein each of the sub memory cells is a DRAM.

7. A semiconductor memory device comprising a memory cell including a plurality of sub memory cells, the plurality of sub memory cells each including:

a first capacitor;

a second capacitor; and

a transistor,

wherein the plurality of sub memory cells are stacked in the memory cell,

wherein the transistor is provided with a first gate and a second gate with a semiconductor film provided therebetween,

wherein the first gate and the second gate are overlap with each other and are electrically connected to each other, and

wherein one of a source and a drain of the transistor is electrically connected to the first capacitor and the second capacitor.

8. The semiconductor memory device according to claim 7, wherein the first capacitor and the second capacitor overlap with each other.

9. The semiconductor memory device according to claim 7, wherein the semiconductor memory device includes a plurality of the memory cells formed in matrix in a plane.

10. The semiconductor memory device according to claim 7, wherein the semiconductor film includes an oxide semiconductor.

11. The semiconductor memory device according to claim 7, wherein the semiconductor memory device further comprises a transistor including silicon and overlapping with the plurality of sub memory cells.

12. The semiconductor memory device according to claim 7, wherein each of the plurality of sub memory cells is a DRAM.