BUCK REGULATION OF A BOOST REGULATOR

• US 20130162234A1
• Filed: 12/27/2012
• Published: 06/27/2013
• Est. Priority Date: 12/27/2011
• Status: Abandoned Application

• Current Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Original Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Inventors: CHIU, Tzu-Huan, CHEN, Jien-Sheng, LI, Chen-Cin
• Application Number:
  US13/728,623
• Publication Number:
  US 20130162234A1
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence

Abstract

Buck regulation methods are provided for a boost regulator to convert an input voltage into an output voltage lower than the input voltage. The buck regulation methods can reduce the variation of the inductor current of the boost regulator, and thereby decrease power consumption and increase the efficiency of the boost regulator under buck regulation.

Claims

1. A buck regulation method for a boost regulator including an inductor connected between an input terminal of the boost regulator and a switching node, a first switch connected between the switching node and a reference potential terminal, and a PMOS transistor connected between the switching node and an output terminal of the boost regulator for use as a second switch, the buck regulation method comprising:

A.) maintaining the first switch off; and

B.) switching the PMOS transistor on and off to convert an input voltage at the input terminal into an output voltage at the output terminal, wherein the output voltage is lower than the input voltage.

2. The buck regulation mode of claim 1, wherein the step B comprises applying a gate voltage to a gate of the PMOS transistor to turn off the PMOS transistor, the gate voltage being greater than a voltage that the input voltage minus an absolute value of a threshold voltage of the PMOS transistor.

3. A buck regulation method for a boost regulator including an inductor connected between an input terminal of the boost regulator and a switching node, a first switch connected between the switching node and a reference potential terminal, and a PMOS transistor connected between the switching node and an output terminal of the boost regulator for use as a second switch, the buck regulation method comprising:

A.) turning off the PMOS transistor and turning on the first switch for charging the inductor;

B.) turning off the first switch and turning on the PMOS transistor; and

C.) turning off both the first switch and the PMOS transistor for discharging the inductor.

4. The buck regulation method of claim 3, wherein the steps A and C comprise applying a gate voltage to a gate of the PMOS transistor, the gate voltage being greater than a voltage that the input voltage minus an absolute value of a threshold voltage of the PMOS transistor.

5. A boost regulator comprising:

an input terminal receiving an input voltage;

an output terminal providing an output voltage;

a reference potential terminal;

a switching node;

an inductor connected between the input terminal and the switching node;

a first switch connected between the switching node and the reference potential terminal;

a PMOS transistor connected between the switching node and the output terminal for use as a second switch; and

a controller connected to the first switch and the PMOS transistor, configured to control the first switch and the PMOS transistor;

wherein when the boost regulator is in a down mode, the controller maintains the first switch off and switches the PMOS transistor on and off to convert the input voltage into the output voltage smaller than the input voltage.

6. The boost regulator of claim 5, wherein when the controller is to turn off the PMOS transistor, it applies a gate voltage to a gate of the PMOS transistor, the gate voltage being greater than a voltage that the input voltage minus an absolute value of a threshold voltage of the PMOS transistor.

7. A boost regulator comprising:

an input terminal receiving an input voltage;

an output terminal providing an output voltage;

a reference potential terminal;

a switching node;

an inductor connected between the input terminal and the switching node;

a first switch connected between the switching node and the reference potential terminal;

a PMOS transistor connected between the switching node and the output terminal for use as a second switch; and

a controller connected to the first switch and the PMOS transistor, configured to control the first switch and the PMOS transistor;

wherein when the boost regulator is in a down mode, the controller executes following steps in sequence;

turning off the PMOS transistor and turning on the first switch for charging the inductor;

turning off the first switch and turning on the PMOS transistor; and

turning off both the first switch and the PMOS transistor for discharging the inductor.

8. The boost regulator of claim 7, wherein when the controller is to turn off the PMOS transistor, it applies a gate voltage to a gate of the PMOS transistor, the gate voltage being greater than a voltage that the input voltage minus an absolute value of a threshold voltage of the PMOS transistor.