Liquid Crystal Display Device

• US 20130162928A1
• Filed: 02/20/2013
• Published: 06/27/2013
• Est. Priority Date: 10/27/2003
• Status: Active Grant

• Current Assignee: Panasonic Intellectual Property Corporation of America (Panasonic Holdings Corporation)
• Original Assignee: Hitachi Displays Limited (Japan Display Incorporated), Panasonic Liquid Crystal Display Company Limited (Panasonic Holdings Corporation)
• Inventors: NAKATANI, Mitsuo, MIWA, Hiroaki, TANAKA, Takao, HIRAI, Sadafumi, KAWABE, Shinichi, ITO, Kazuyuki, IEDA, Masahiro, ASHIZAWA, Keiichiro, SASAKI, Makoto
• Granted Patent: US 8,724,072 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: G02F 1/13396 Spacers having different sizes
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence

Abstract

A liquid crystal display device with a pair of substrates which are arranged to face each other with liquid crystal therebetween, columnar spacers having the substantially equal height formed on a liquid-crystal-side surface of one substrate, and the columnar spacers include the columnar spacer which is contact with a liquid-crystal-side surface of another substrate and the columnar spacer which is not contact with the liquid-crystal-side surface of another substrate.

Claims

1. A liquid crystal device, comprising:

a first substrate and a second substrate which are arranged to face each other with a liquid crystal layer there between;

a plurality of gate signal lines and a plurality of drain signal lines formed on the first substrate;

a plurality of pixel regions defined by the drain signal lines and the gate signal liens;

at least a thin film transistor formed on the first substrate in each pixel region, each thin film transistor having a first semiconductor layer;

a plurality of column spaces formed on the second substrate including first columnar spacers and second columnar spaces, the columnar spacers being formed on all of the gate singal lines in plain view; and

a second semiconductor layer formed on the gate signal lines, and

wherein the first columnar spacers contact to the first substrate side of the second substrate and the second columnar spacers do not contact to the first substrate side of the second substrate, the first columnar spacers and the second columnar spacers are arrangted on the gate signal lines, the first colunar spacers are arranged in a formation region of the second semiconductor layers, and the second colunmnar spacers are aranged in a non-formation region of the second semiconductor layers.

2. A liquid crystal display device, comprising:

a first substrate and a second substrate which are arranged to face each other with a liquid crystal layer there between;

a plurality of gate signal lines and a plurality of drain signal lines formed on the first substrate;

a plurality of pixel regions defined by the drain signal liens and the gate signal lines;

at least a thin film transistor formed on the first substrate in each pixel region, each thin film transistor having a first semiconductor layer;

a plurality of columnar spaces formed on the second substrate including first columnar spacers and second columnar spacers, the columnar spacers being formed on all of the gate signal lines in plain view;

isolate conducting layers formed on the gate singal lines, and

wherein the first colunar spacers contact to the first substrate side of the second substrate and the second columnar spacers do not contact to the first substrate side of the second substrate, the first columnar spacers and the second columnar spacers are arranged on the gate signal lines, the first columnar spacers are arranged on the gate signal lines, the first columnar spacers are arranged in a formation region of the isolated conducting layers, and the second columnar spacers are arranged in a non-formation region of the isolated conducting layers.