APPARATUSES AND METHODS INCLUDING MEMORY WITH TOP AND BOTTOM DATA LINES

• US 20130163305A1
• Filed: 12/22/2011
• Published: 06/27/2013
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Granted Patent: US 8,792,263 B2
• Time in Patent Office: Days
• US Class Current: 365/72
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and second set of data lines. Other embodiments including additional apparatuses and methods are described.

Claims

1. An apparatus comprising:

a first set of data lines;

a second set of data lines; and

memory cells located in different levels of the apparatus and arranged in memory cell strings between the first and second sets of data lines.

2. The apparatus of claim 1, further comprising a first source line and a second source line, wherein a first portion of the memory cell strings is coupled to the first source line and the first set of data lines, and a second portion of the memory cell strings is coupled to the second source line and the second set of data lines.

3. The apparatus of claim 2, wherein the first source line is located between the first portion of the memory cell strings and the second set of data lines.

4. The apparatus of claim 3, wherein the second source line is located between the second portion of the memory cell strings and the first set of data lines.

5. The apparatus of claim 1, further including a substrate, wherein one of the first and second sets of data lines is located between the substrate and the memory cells.

6. The apparatus of claim 1, wherein the apparatus comprises a memory device.

7. The apparatus of claim 1, wherein the apparatus comprises a system including a memory device that includes the data lines and the memory cells.

8. An apparatus comprising:

a first data line located on a first level of the apparatus;

a second data line located on a second level of the apparatus;

a first memory cell string coupled to the first data line;

a second memory cell string coupled to the second data line; and

a module configured to select the first and second memory cell strings in an operation of the apparatus.

9. The apparatus of claim 8, wherein the first memory cell string includes a first memory cell, the second memory cell string includes a second memory cell, and the module is configured to concurrently store information into the first and second memory cells.

10. The apparatus of claim 8, wherein the first memory cell string includes a first memory cell, the second memory cell string includes a second memory cell, and the module is configured to concurrently retrieve information from the first and second memory cells.

11. The apparatus of claim 8, further comprising:

a first transistor coupled between the first memory cell string and the first data line;

a first select line to provide a signal to control the first transistor;

a second transistor coupled between the second memory cell string and the second data line; and

a second select line to provide a signal to control the first transistor.

12. The apparatus of claim 11, wherein the first select line is coupled to the second select line.

13. The apparatus of claim 8, further comprising:

a third data line located on the first level of the apparatus;

a third memory cell string coupled to the third data line;

a fourth data line located on the second level of the apparatus;

a fourth memory cell string coupled to the fourth data line; and

wherein the module is configured to select the third and fourth memory cell strings in the operation of the apparatus.

14. The apparatus of claim 13, wherein the module is configured to concurrently store information into a first memory cell included in the first memory cell string, a second memory cell included in the second memory cell string, a third memory cell included in the third memory cell string, and a fourth memory cell included in the fourth memory cell string in the operation of the apparatus.

15. The apparatus of claim 11, wherein the module is configured to concurrently retrieve information from a first memory cell included in the first memory cell string, a second memory cell included in the second memory cell string, a third memory cell included in the third memory cell string, and a fourth memory cell included in the fourth memory cell string in the operation of the apparatus.

16. An apparatus comprising:

memory cells arranged in rows including a first row and a second row, the memory cells including a first memory cell set located in the first row and a second memory cell set located in the second row;

a first set of data lines;

a second set of data lines; and

a module configured to perform at least one of concurrently retrieve information from the first and second memory cell sets through the first and second sets of data lines in a first operation of the apparatus, and concurrently store information into the first and second memory cell sets through the first and second sets of data lines in a second operation of the apparatus.

17. The apparatus of claim 16, further comprising additional memory cells, wherein the memory cells and the additional memory cells are located on different levels of the apparatus, the additional memory cells arranged in rows including a third row and a fourth row, the additional memory cells including a third memory cell set located in the third row and a fourth memory cell set located in the fourth row, wherein the module is configured to concurrently retrieve information from the third and fourth memory cell sets through the first and second sets of data lines.

18. The apparatus of claim 16, further comprising an access line shared by the first and second memory cell sets.

19. The apparatus of claim 18, further comprising an additional access line shared by the third and fourth memory cell sets.

20. The apparatus of claim 16, wherein the memory cells are located in a same level of the apparatus.

21. The apparatus of claim 16, wherein the first and second memory cell sets include an equal quantity of memory cells.

22. A method comprising:

selecting a first memory cell string associated with a first data line of a device in an operation of the device, the first data line located on a first level of the device; and

selecting a second memory cell string associated with a second data line of the device in the operation of the device, the second data line located on a second level of the device.

23. The method of claim 22, wherein the operation includes one of a read operation and a write operation.

24. The method of claim 22, further comprising:

retrieving information from a first memory cell in the first memory cell string through the first data line; and

retrieving information from a second memory cell in the second memory cell string through the second data line.

25. The method of claim 24, wherein retrieving the information from the first memory cell and retrieving the information from the second memory cell are performed concurrently.

26. The method of claim 24, further comprising:

storing information into the first memory cell in an additional operation of the device; and

storing information into the second memory cell in the additional operation of the device.

27. The method of claim 26, wherein storing the information into the first memory cell and storing information into the second memory cell are performed concurrently.

28. A method comprising:

selecting first memory cell strings associated with a first set of data lines in an operation of a device, the first memory cell strings including a first memory cell set located in a first row of memory cells of the device;

selecting second memory cell strings associated with a second set of data lines in the operation of the device, the second memory cell strings including a second memory cell set located in a second row of memory cells of the device; and

performing at least one of a first operation and a second operation, wherein performing the first operation includes concurrently storing information into the first and second memory cell sets, and performing the second operation includes concurrently retrieving information from the first and second memory cell sets.

29. The method of claim 28, wherein an amount of information stored into the first memory cell set is equal to an amount of information stored into the second memory cell set.

30. The method of claim 28, wherein an amount of information retrieved from the first memory cell set is equal to an amount of information retrieved from the second memory cell set.

31. The method of claim 28, wherein concurrently storing information into the first and second memory cell sets includes storing multiple bits of information into the first and second memory cell sets, such that a first bit among the multiple bits is stored into a memory cell included in the first memory cell set while a second bit among the multiple bits is stored into a second memory cell included in the second memory cell set.

32. The method of claim 28, wherein concurrently retrieving information from the first and second memory cell sets includes retrieving multiple bits of information from the first and second memory cell sets, such that a first bit among the multiple bits is retrieved from a memory cell included in the first memory cell set while a second bit among the multiple bits is retrieved from a second memory cell included in the second memory cell set.