HIGHLY SELECTIVE SPACER ETCH PROCESS WITH REDUCED SIDEWALL SPACER SLIMMING

• US 20130164940A1
• Filed: 12/23/2011
• Published: 06/27/2013
• Est. Priority Date: 12/23/2011
• Status: Active Grant

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: OHTAKE, Hiroto, RALEY, Anglique Denise, MORI, Takuya
• Granted Patent: US 8,664,125 B2
• Time in Patent Office: Days
• US Class Current: 438/696
• CPC Class Codes: H01J 37/32192 Microwave generated discharge H01J37/32357, H01J37/32366, H01J37/32394, H01J37/32403 take precedence
• CPC Class Codes: H01J 37/3222 Antennas
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/3115 Doping the insulating layers
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.

Claims

1. A method for performing a spacer etch process, comprising:

conformally applying a spacer material over a gate structure on a substrate; and

performing a spacer etch process sequence to partially remove said spacer material from a capping region of said gate structure and a substrate region on said substrate adjacent a base of said gate structure, while retaining a spacer sidewall positioned along a sidewall of said gate structure, said spacer etch process sequence comprising;

oxidizing an exposed surface of said spacer material to form a spacer oxidation layer,

performing a first etching process to anisotropically remove said spacer oxidation layer from said spacer material at said substrate region on said substrate and said spacer material at said capping region of said gate structure, while substantially retaining said spacer oxidation layer on said spacer material along said sidewall of said gate structure, and

performing a second etching process to selectively remove said spacer material from said substrate region on said substrate and said capping region of said gate structure to leave behind said spacer sidewall on said sidewall of said gate structure.

2. The method of claim 1, wherein said spacer material comprises silicon nitride (Si_xN_z), silicon carbide (Si_xC_y), or silicon carbonitride (Si_xC_yN_z).

3. The method of claim 2, wherein said spacer material conformally applied over said gate structure has a thickness less than or equal to about 10 nanometers (nm).

4. The method of claim 1, wherein said oxidizing said exposed surface of said spacer material comprises exposing said spacer material to an oxygen-containing environment.

5. The method of claim 4, wherein said oxygen-containing environment contains an oxygen-containing plasma.

6. The method of claim 4, wherein said oxygen-containing environment contains O, O₂, O₃, CO, CO₂, NO, N₂O, or NO₂, or any combination of two or more thereof.

7. The method of claim 1, wherein said performing said first etching process comprises forming plasma from a first etching process composition containing a halomethane gas and a noble gas.

8. The method of claim 7, wherein said performing said first etching process comprises:

introducing said first etching process composition containing CF₄ and Ar to a plasma processing system,

setting a pressure in said plasma processing system at or less than about 50 mTorr,

forming a first etching plasma from said first etching process composition, and

exposing said substrate to said first etching plasma.

9. The method of claim 8, wherein said performing said first etching process further comprises:

forming said first etching plasma by coupling electromagnetic (EM) radiation from a radial line slot antenna (RLSA) to said first etching process composition, and

applying an electrical bias to said substrate by coupling radio frequency (RF) power to a substrate holder upon which said substrate rests.

10. The method of claim 9, wherein said forming said first etching plasma comprises coupling electromagnetic (EM) energy at a microwave frequency in a desired EM wave mode to said first etching plasma by generating a surface wave on a plasma surface of an EM wave launcher adjacent said first etching plasma, said EM wave launcher comprises a slot antenna having a plurality of slots formed there through configured to couple said EM energy from a first region above said slot antenna to a second region below said slot antenna.

11. The method of claim 1, wherein said performing said second etching process comprises forming plasma from a second etching process composition containing a halomethane gas, an oxygen-containing gas, and a noble gas.

12. The method of claim 11, wherein said performing said second etching process comprises:

introducing said second etching process composition containing CH₃F, O₂, and Ar to a plasma processing system,

setting a pressure in said plasma processing system at or greater than about 50 mTorr,

forming a second etching plasma from said second etching process composition, and

exposing said substrate to said second etching plasma.

13. The method of claim 12, wherein said performing said second etching process further comprises:

forming said second etching plasma by coupling EM radiation from a radial line slot antenna (RLSA) to said second etching process composition, and

applying an electrical bias to said substrate by coupling RF power to a substrate holder upon which said substrate rests.

14. The method of claim 13, wherein said forming said second etching plasma comprises coupling electromagnetic (EM) energy at a microwave frequency in a desired EM wave mode to said second etching plasma by generating a surface wave on a plasma surface of an EM wave launcher adjacent said first etching plasma, said EM wave launcher comprises a slot antenna having a plurality of slots formed there through configured to couple said EM energy from a first region above said slot antenna to a second region below said slot antenna.

15. The method of claim 1, further comprising:

selecting process conditions for said spacer etch process sequence to achieve a substrate recess at said substrate region on said substrate adjacent said base of said gate structure having a value of 1.5 nm or less.

16. The method of claim 1, further comprising:

selecting process conditions for said spacer etch process sequence to achieve a substrate recess at said substrate region on said substrate adjacent said base of said gate structure having a value of 1 nm or less.

17. The method of claim 1, further comprising:

selecting process conditions for said spacer etch process sequence to achieve a top recess at said top of said sidewall space on said gate structure having a value of 5 nm or less.

18. The method of claim 1, further comprising:

selecting process conditions for said spacer etch process sequence to achieve a CD reduction of said sidewall spacer having a value of 2 nm or less.

19. The method of claim 1, further comprising:

selecting process conditions for said spacer etch process sequence to achieve substantially no footing at said base of said gate structure.

20. A method for performing a spacer etch process, comprising:

receiving a substrate having a spacer material conformally applied over a gate structure on said substrate; and

performing a spacer etch process sequence to partially remove said spacer material from a capping region of said gate structure and a substrate region on said substrate adjacent a base of said gate structure, while retaining a spacer sidewall positioned along a sidewall of said gate structure, said spacer etch process sequence comprising;

oxidizing an exposed surface of said spacer material to form a spacer oxidation layer,

performing a first etching process to anisotropically remove said spacer oxidation layer from said spacer material at said substrate region on said substrate and said spacer material at said capping region of said gate structure, while substantially retaining said spacer oxidation layer on said spacer material along said sidewall of said gate structure, and

performing a second etching process to selectively remove said spacer material from said substrate region on said substrate and said capping region of said gate structure to leave behind said spacer sidewall on said sidewall of said gate structure.