Method Of Controlling Non-Volatile Memory, Non-Volatile Memory Controller Therefor, And Memory System Including The Same

• US 20130166825A1
• Filed: 09/14/2012
• Published: 06/27/2013
• Est. Priority Date: 12/27/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Du-Won Hong, Jin Yeong Kim
• Inventors: KIM, Jin Yeong, HONG, Du-Won
• Granted Patent: US 8,954,708 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

A method of controlling a non-volatile memory device having multiple planes including receiving write requests from a host, the write requests each including a logical address, a write command, and a data set; storing the data sets at an address of a buffer; storing the buffer address in a mapping table that maps addresses of the buffer to the multiple planes; sequentially transmitting the data sets stored at respective buffer addresses to page buffers, respectively, of the planes corresponding to the buffer addresses according to the mapping table; and programming in parallel at least two data sets stored in respective page buffers to memory cells of the non-volatile memory device.

Claims

1. A method of controlling a non-volatile memory device including multiple planes, the method comprising:

receiving a write request from a host, the write request including a data set;

storing the data set at a buffer address in a buffer;

storing the buffer address in a mapping table, the mapping table configured to map the buffer addresses to the multiple planes, and the buffer address corresponding to where the data set is stored;

sequentially transmitting data sets stored at respective buffer addresses to page buffers of the planes corresponding to the buffer addresses according to the mapping table; and

programming in parallel at least two data sets stored in respective page buffers to memory cells of the non-volatile memory device.

2. The method of claim 1, wherein the number of multiple planes is at least two.

3. The method of claim 1, wherein the write request is a random write request.

4. The method of claim 1, wherein

the sequentially transmitting data sets, sequentially transmits as many data sets as the number of the multiple planes from the buffer to the page buffers of the planes, respectively, if a number of the data sets stored in the buffer is at least a number of the multiple planes, and

the programming in parallel programs the data sets simultaneously to the memory cells, if the number of the data sets stored in the respective page buffers equals the number of the multiple planes.

5. The method of claim 1, further comprising:

setting a start time if a data set received from the host and stored in the buffer corresponds to a desired plane among the multiple planes; and

checking whether a time limit has elapsed from the start time.

6. The method of claim 5, further comprising:

performing a multi-plane program operation on data sets less than the number of the multiple planes, if, after the time limit has elapsed, a number of the data sets stored in the buffer is less than the number of the multiple planes.

7. The method of claim 6, wherein the performing the multi-plane program operation on the data sets less than the number of the multiple planes comprises:

sequentially storing the data sets in page buffers, respectively, of corresponding planes of the non-volatile memory device; and

programming in parallel the data sets, which are valid and stored in the page buffers, and at least one invalid data set, which is respectively stored in at least one page buffer of at least one uncorresponding plane, in the memory cells.

8. The method of claim 6, wherein the performing the multi-plane program operation on the data sets less than the number of the multiple planes comprises:

sequentially storing as many data sets as a maximum number of available planes among the data sets stored in the buffer in page buffers of corresponding planes of the non-volatile memory device;

programming in parallel as many of the data sets as the maximum number of available planes in the memory cells;

storing a data set remaining in the buffer in a page buffer of a corresponding plane of the non-volatile memory device; and

programming the data set stored in the page buffer, wherein

the maximum number of available planes is a maximum value among values less than the number of the data stored in the buffer among the numbers of planes that the non-volatile memory device can perform a program operation on simultaneously.

9. The method of claim 1, wherein the mapping table stores a buffer address corresponding to each plane and the mapping table is updated if the data set is stored in the buffer.

10. A recording medium for recording a computer program for executing the method of claim 1.

11. A method of controlling a non-volatile memory device including multiple planes, the method comprising:

storing, in a buffer, a data of as many valid pages as a number of the multiple planes from the non-volatile memory device;

storing a buffer address in a mapping table, the buffer address corresponding to where the data of each valid page is stored, the mapping table configured to map the buffer address to each of the planes; and

performing a multi-plane program operation on the data of the valid page stored at each buffer address according to the mapping table.

12. The method of claim 11, wherein the performing the multi-plane program operation comprises:

sequentially transmitting the data of the valid pages from the buffer to page buffers, respectively, of the respective planes; and

simultaneously programming the data in the page buffers based on a physical address associated with the data.

13. A memory system comprising:

a buffer memory;

a non-volatile memory device including multiple planes; and

a memory controller configured to,

receive a plurality of write requests, each write request including a logical address and a data set from a host,

store the data sets in the buffer memory in response to the write request, the data sets having logical addresses that are not sequential, and

perform a multi-plane program operation to program the data sets stored in the buffer memory in the non-volatile memory device.

14. The memory system of claim 13, wherein the memory controller comprises:

a mapping table including buffer address information corresponding to each of the multiple planes.

15. The memory system of claim 14, wherein the multiple planes comprise four planes that each respectively include one of the first through fourth pages, each page having the same or different row addresses,

the memory controller is configured to control a first data set corresponding to a first logical address to be stored in the first page;

the memory controller is configured to control a second data set corresponding to a second logical address to be stored in the second page;

the memory controller is configured to control a third data set corresponding to a third logical address to be stored in the third page;

the memory controller is configured to control a fourth data set corresponding to a fourth logical address to be stored in the fourth page; and

at least two logical addresses among the first through the fourth logical address are not sequential.

16. The memory system of claim 15, wherein the memory controller sequentially transmits the first through fourth data sets from the buffer memory to page buffers, respectively, of the respective multiple planes with reference to the mapping table;

and

the first through fourth data sets stored in the respective page buffers are simultaneously programmed to the first through fourth pages, respectively.

17. The memory system of claim 13, wherein the memory controller performs the multi-plane program operation, if a number of data sets stored in the buffer memory is at least a number of multiple planes.

18. The memory system of claim 13, wherein the memory controller comprises:

a timer configured to count a duration from a start time, the start time being when a data set stored in the buffer memory corresponds to a desired one of the multiple planes, and wherein

the memory controller is configured to perform the multi-plane program operation irrespective of whether the number of the data sets stored in the buffer memory is less than a number of multiple planes, if the duration counted by the timer exceeds a time limit.

19. The memory system of claim 13, wherein the memory system is one of a memory card, a memory drive, and a solid state drive (SSD).

20. A memory controller configured to control a non-volatile memory device, the memory controller comprising:

a buffer memory configured to store data sets received from a host; and

a central processing unit (CPU) configured to control the non-volatile memory device to perform a multi-plane program operation to program the data sets stored in the buffer memory in the non-volatile memory device, in response to a write request, the write request including a logical address and a data set from the host,

wherein the data sets subjected to the multi-plane program operation have logical addresses that are not sequential.

21. The memory controller of claim 20, further comprising:

a mapping table configured to store buffer address information corresponding to each of the multiple planes.

22. The memory controller of claim 20, further comprising:

a timer configured to set a start time count, if a data set, which is received from the host and stored in the buffer memory, corresponds to a desired plane among the multiple, and wherein the CPU is configured to check whether a time limit has elapsed from the start time.

23. The memory controller of claim 20, wherein the CPU performs a multi-plane program operation on data sets less than the number of the multiple planes, if at the time limit, the number of the data sets stored in the buffer is less than the number of the multiple planes.

24. The memory controller of claim 20, wherein, the CPU performs the multi-plane program operation, if the number of data sets stored in the buffer memory is at least a number of multiple planes.

25. A method of controlling a non-volatile memory device via a memory controller, the non-volatile memory device having multiple planes, each plane including a page buffer, and the memory controller including a buffer memory configured to store a plurality of data sets corresponding to non-sequential logical addresses, the method comprising:

receiving, at the memory controller, a plurality of write requests, each write request including a logical address and a data set of the plurality of data sets;

storing each of the data sets at an address of the buffer memory;

sequentially transmitting a number of data sets of the plurality of data sets less than or equal to a number of the planes, from the address of the buffer memory to the page buffer of a plane according to a mapping table, the mapping table mapping the addresses of the buffer memory to the planes; and

programming, in parallel, the plurality of data sets from the page buffer to memory cells of the non-volatile memory device according to a physical address corresponding to the logical address associated with the data set.

26. The method of claim 25, wherein the number of data sets sequentially transmitted is less than the number of the planes, if a duration of time passes after the one or more data sets are stored at the buffer memory.

27. The method of claim 25, wherein the plurality of data sets include first through fourth data sets and the planes include at least four planes that have at least four pages, the method further comprising:

sequentially transmitting the first through fourth data sets from the buffer memory to the page buffer of a respective one of the four planes according to the mapping table; and

programming, simultaneously, the first through fourth data sets stored in the page buffers to a first through fourth page of the at least four pages, respectively.