BORDERLESS CONTACT STRUCTURE EMPLOYING DUAL ETCH STOP LAYERS
First Claim
1. A semiconductor structure comprising:
- at least one gate structure located on a semiconductor substrate, wherein each of said at least one gate structure includes, from bottom to top, a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric;
a second etch stop layer located on said at least one gate structure;
a first contact-level dielectric layer and a second contact-level dielectric layer located over said second etch stop layer;
at least one gate contact via structure embedded in said first and second contact-level dielectric layers, wherein each of said at least one gate contact via structure extends through said first and second contact-level dielectric layers, said second etch stop layer, one of said at least one gate cap dielectric, and one of said at least one first etch stop layer; and
at least one source/drain contact via structure embedded in said first and second contact-level dielectric layers, wherein each of said at least one source/drain contact via structure extends through said first and second contact-level dielectric layers and said second etch stop layer.
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Abstract
Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed.
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Citations
20 Claims
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1. A semiconductor structure comprising:
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at least one gate structure located on a semiconductor substrate, wherein each of said at least one gate structure includes, from bottom to top, a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric; a second etch stop layer located on said at least one gate structure; a first contact-level dielectric layer and a second contact-level dielectric layer located over said second etch stop layer; at least one gate contact via structure embedded in said first and second contact-level dielectric layers, wherein each of said at least one gate contact via structure extends through said first and second contact-level dielectric layers, said second etch stop layer, one of said at least one gate cap dielectric, and one of said at least one first etch stop layer; and at least one source/drain contact via structure embedded in said first and second contact-level dielectric layers, wherein each of said at least one source/drain contact via structure extends through said first and second contact-level dielectric layers and said second etch stop layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification