INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS, AND DESIGN STRUCTURE THEREOF

• US 20130168807A1
• Filed: 02/28/2013
• Published: 07/04/2013
• Est. Priority Date: 05/09/2008
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: HSU, Louis L., TONTI, William R., YANG, Chih-Chao
• Granted Patent: US 8,692,375 B2
• Time in Patent Office: Days
• US Class Current: 257/529
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Claims

1. An interconnect structure comprising:

a first macro having a first e-fuse programmability comprising an upper wiring layer capped by a first capping material; and

a second macro having a second e-fuse programmability comprising an upper wiring layer capped by a second capping material having interfacial properties which are different than that of the first macro.

2. The interconnect structure of claim 1, wherein the first macro further includes an interface comprising the upper wiring layer and the first capping material,

the second macro further includes an interface comprising the upper wiring layer and the second capping material, and

the first capping material is different than the second capping material.

3. The interconnect structure of claim 2, wherein the first capping material comprises SiN and the second capping material comprises one of:

Co(W,P,B), Ru, Ir, Rh and Pt.

4. The interconnect structure of claim 2, wherein the second capping material and/or the upper wiring layer of the second macro is damaged to degrade adhesion between the second capping material and the upper wiring layer of the second macro.

5. The interconnect structure of claim 1, wherein the first capping material and the second capping material is a same material, and the second capping material and/or the upper wiring layer of the second macro is damaged thereby providing a degraded electromigration (EM) resistance than that of the first macro.

6. The interconnect structure of claim 5, wherein the second capping material and/or the upper wiring layer of the second macro is damaged by radiation.

7. The interconnect structure of claim 6, wherein the radiation is provided by an e-beam, a ultraviolet light, a visible light, or a laser light.

8. The interconnect structure of claim 1, wherein the first macro further includes an interface comprising the upper wiring layer and the first capping material,

the second macro further includes an interface comprising the upper wiring layer and the second capping material, and

the second capping material and/or the upper wiring layer of the second macro is damaged thereby exhibiting degraded interfacial properties between the metal wiring layer and the second capping material.

9. The interconnect structure of claim 1, wherein the first capping material is different than the second capping material.

10. The interconnect structure of claim 1, wherein the first macro further includes an interface comprising the upper wiring layer and the first capping material,

the second macro further includes an interface comprising the upper wiring layer and the second capping material, and

the interconnect structure further comprises a third macro having a third e-fuse programmability comprising an upper wiring layer capped by a third capping material having interfacial properties which are different than that of the first macro and the second macro.

11. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a first macro having a first interfacial structure; and

a second macro having a second interfacial structure, different from the first interfacial structure.

12. The design structure of claim 11, wherein the design structure comprises a netlist.

13. The design structure of claim 11, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

14. The design structure of claim 11, wherein the design structure resides in a programmable gate array.

15. The design structure of claim 11, wherein the first interfacial structure comprises a first upper wiring layer and a first capping material, and

the second interfacial structure comprises a second upper wiring layer and a second capping material.

16. The design structure of claim 15, wherein the first capping material is different than the second capping material.

17. The design structure of claim 15, wherein the first capping material and the second capping material is a same material, and the second capping material and/or the second upper wiring layer is damaged thereby providing a degraded electromigration (EM) resistance than that of the first macro.

18. The deign structure of claim 15, wherein the second capping material and/or the second upper wiring layer is damaged to degrade adhesion between the second capping material and the second upper wiring layer.