PACKING MULTIPLE SHADER PROGRAMS ONTO A GRAPHICS PROCESSOR

• US 20130169642A1
• Filed: 12/07/2012
• Published: 07/04/2013
• Est. Priority Date: 12/29/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Frascati, Christopher Paul, Seetharamaiah, Avinash, Blankenship, Joseph
• Granted Patent: US 9,530,245 B2
• Time in Patent Office: Days
• US Class Current: 345/426
• CPC Class Codes: G06F 9/445 Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: G06F 9/44594 Unloading
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 11/00 2D [Two Dimensional] image generation
• CPC Class Codes: G06T 15/04 Texture mapping
• CPC Class Codes: G06T 15/80 Shading
• CPC Class Codes: G06T 15/83 Phong shading
• CPC Class Codes: G06T 17/10 Constructive solid geometry [CSG] using solid primitives, e.g. cylinders, cubes
• CPC Class Codes: G06T 17/20 Finite element generation, e.g. wire-frame surface description, tesselation
• CPC Class Codes: G06T 7/40 Analysis of texture depth or shape recovery from texture G06T7/529

Abstract

This disclosure describes techniques for packing multiple shader programs of a common shader program type onto a graphics processing unit (GPU). The techniques may include, for example, causing a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time. In addition, various techniques for evicting shader programs from an on-chip shader program instruction memory are described.

Claims

1. A method comprising:

causing a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time.

2. The method of claim 1, wherein the common shader program type comprises a shader program type that is indicative of at least one of a type of data upon which the shader program is configured to operate and a type of operation performed by the shader program.

3. The method of claim 1, wherein the common shader program type comprises one of a vertex shader program type, a pixel shader program type, a geometry shader program type, a hull shader program type, a domain shader program type, and a compute shader program type.

4. The method of claim 1, wherein causing the plurality of shader programs of the common shader program type to be loaded comprises:

loading a first shader program of a shader program type into the on-chip shader program instruction memory; and

loading a second shader program of the shader program type into the on-chip shader program instruction memory without overwriting the first shader program.

5. The method of claim 1, wherein causing the plurality of shader programs of the common shader program type to be loaded comprises:

loading a first shader program of a shader program type into the on-chip shader program instruction memory;

determining one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory; and

loading a second shader program of the shader program type into one of the one or more ranges of available memory space.

6. The method of claim 1, further comprising:

determining whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory; and

in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program, evicting a shader program from the on-chip shader program instruction memory.

7. The method of claim 6, wherein evicting the shader program from the on-chip shader program instruction memory comprises:

determining a least frequently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory; and

evicting the least frequently used shader program from the on-chip shader program instruction memory.

8. The method of claim 6, wherein evicting the shader program from the on-chip shader program instruction memory comprises:

determining a least recently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory; and

evicting the least recently used shader program from the on-chip shader program instruction memory.

9. The method of claim 6, wherein evicting the shader program from the on-chip shader program instruction memory comprises:

determining a set of N least frequently used shader programs from a set of one or more shader programs stored within the on-chip shader program instruction memory, where N is an integer greater than or equal to one;

determining a least recently used shader program from the set of N least frequently used shader programs; and

evicting the least recently used shader program from the on-chip shader program instruction memory.

10. The method of claim 6, wherein evicting the shader program from the on-chip shader program instruction memory comprises:

overwriting at least a portion of the evicted shader program with at least a portion of the shader program to be loaded into the on-chip shader program instruction memory.

11. A device comprising:

a processor configured to cause a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time.

12. The device of claim 11, wherein the common shader program type comprises a shader program type that is indicative of at least one of a type of data upon which the shader program is configured to operate and a type of operation performed by the shader program.

13. The device of claim 11, wherein the common shader program type comprises one of a vertex shader program type, a pixel shader program type, a geometry shader program type, a hull shader program type, a domain shader program type, and a compute shader program type.

14. The device of claim 11, wherein the processor is further configured to load a first shader program of a shader program type into the on-chip shader program instruction memory, and load a second shader program of the shader program type into the on-chip shader program instruction memory without overwriting the first shader program.

15. The device of claim 11, wherein the processor is further configured to load a first shader program of a shader program type into the on-chip shader program instruction memory, determine one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory, and load a second shader program of the shader program type into one of the one or more ranges of available memory space.

16. The device of claim 11, wherein the processor is further configured to determine whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory, and evict a shader program from the on-chip shader program instruction memory in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program.

17. The device of claim 16, wherein the processor is further configured to determine a least frequently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory, and evict the least frequently used shader program from the on-chip shader program instruction memory.

18. The device of claim 16, wherein the processor is further configured to determine a least recently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory, and evict the least recently used shader program from the on-chip shader program instruction memory.

19. The device of claim 16, wherein the processor is further configured to determine a set of N least frequently used shader programs from a set of one or more shader programs stored within the on-chip shader program instruction memory, determine a least recently used shader program from the set of N least frequently used shader programs, and evict the least recently used shader program from the on-chip shader program instruction memory, where N is an integer greater than or equal to one.

20. The device of claim 16, wherein the processor is further configured to overwrite at least a portion of the evicted shader program with at least a portion of the shader program to be loaded into the on-chip shader program instruction memory.

21. The device of claim 16, wherein the device comprises a wireless communication device.

22. The device of claim 16, wherein the device comprises a mobile phone handset.

23. An apparatus comprising:

means for loading a shader program into an on-chip shader program instruction memory of a graphics processor; and

means for causing a plurality of shader programs of a common shader program type to be loaded into the on-chip shader program instruction memory of the graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time.

24. The apparatus of claim 23, wherein the common shader program type comprises a shader program type that is indicative of at least one of a type of data upon which the shader program is configured to operate and a type of operation performed by the shader program.

25. The apparatus of claim 23, wherein the common shader program type comprises one of a vertex shader program type, a pixel shader program type, a geometry shader program type, a hull shader program type, a domain shader program type, and a compute shader program type.

26. The apparatus of claim 23, wherein the means for causing the plurality of shader programs of the common shader program type to be loaded comprises:

means for loading a first shader program of a shader program type into the on-chip shader program instruction memory; and

means for loading a second shader program of the shader program type into the on-chip shader program instruction memory without overwriting the first shader program.

27. The apparatus of claim 23, wherein the means for causing the plurality of shader programs of the common shader program type to be loaded comprises:

means for loading a first shader program of a shader program type into the on-chip shader program instruction memory;

means for determining one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory; and

means for loading a second shader program of the shader program type into one of the one or more ranges of available memory space.

28. The apparatus of claim 23, further comprising:

means for determining whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory; and

means for evicting a shader program from the on-chip shader program instruction memory in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program.

29. The apparatus of claim 28, wherein the means for evicting the shader program from the on-chip shader program instruction memory comprises:

means for determining a least frequently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory; and

means for evicting the least frequently used shader program from the on-chip shader program instruction memory.

30. The apparatus of claim 28, wherein the means for evicting the shader program from the on-chip shader program instruction memory comprises:

means for determining a least recently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory; and

means for evicting the least recently used shader program from the on-chip shader program instruction memory.

31. The apparatus of claim 28, wherein the means for evicting the shader program from the on-chip shader program instruction memory comprises:

means for determining a set of N least frequently used shader programs from a set of one or more shader programs stored within the on-chip shader program instruction memory, where N is an integer greater than or equal to one;

means for determining a least recently used shader program from the set of N least frequently used shader programs; and

means for evicting the least recently used shader program from the on-chip shader program instruction memory.

32. The apparatus of claim 28, wherein the means for evicting the shader program from the on-chip shader program instruction memory comprises:

means for overwriting at least a portion of the evicted shader program with at least a portion of the shader program to be loaded into the on-chip shader program instruction memory.

33. A computer-readable storage medium storing instructions that, when executed, cause one or more processors to:

cause a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time.

34. The computer-readable storage medium of claim 33, wherein the common shader program type comprises a shader program type that is indicative of at least one of a type of data upon which the shader program is configured to operate and a type of operation performed by the shader program.

35. The computer-readable storage medium of claim 33, wherein the common shader program type comprises one of a vertex shader program type, a pixel shader program type, a geometry shader program type, a hull shader program type, a domain shader program type, and a compute shader program type.

36. The computer-readable storage medium of claim 33, wherein the instructions that cause the one or more processors to cause the plurality of shader programs of the common shader program type to be loaded comprise instructions that cause the one or more processors to:

load a first shader program of a shader program type into the on-chip shader program instruction memory; and

load a second shader program of the shader program type into the on-chip shader program instruction memory without overwriting the first shader program.

37. The computer-readable storage medium of claim 33, wherein the instructions that cause the one or more processors to cause the plurality of shader programs of the common shader program type to be loaded comprise instructions that cause the one or more processors to:

load a first shader program of a shader program type into the on-chip shader program instruction memory;

determine one or more ranges of available memory space in the on-chip shader program instruction memory after the first shader program has been loaded into the on-chip shader program instruction memory; and

load a second shader program of the shader program type into one of the one or more ranges of available memory space.

38. The computer-readable storage medium of claim 33, further comprising instructions that cause the one or more processors to:

determine whether the on-chip shader program instruction memory has a sufficient amount of available memory space to store a shader program to be loaded into the on-chip shader program instruction memory; and

in response to determining that the on-chip shader program instruction memory does not have the sufficient amount of available memory space to store the shader program, evict a shader program from the on-chip shader program instruction memory.

39. The computer-readable storage medium of claim 38, wherein the instructions that cause the one or more processors to evict the shader program from the on-chip shader program instruction memory comprise instructions that cause the one or more processors to:

determine a least frequently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory; and

evict the least frequently used shader program from the on-chip shader program instruction memory.

40. The computer-readable storage medium of claim 38, wherein the instructions that cause the one or more processors to evict the shader program from the on-chip shader program instruction memory comprise instructions that cause the one or more processors to:

determine a least recently used shader program from a set of one or more shader programs stored within the on-chip shader program instruction memory; and

evict the least recently used shader program from the on-chip shader program instruction memory.

41. The computer-readable storage medium of claim 38, wherein the instructions that cause the one or more processors to evict the shader program from the on-chip shader program instruction memory comprise instructions that cause the one or more processors to:

determine a set of N least frequently used shader programs from a set of one or more shader programs stored within the on-chip shader program instruction memory, where N is an integer greater than or equal to one;

determine a least recently used shader program from the set of N least frequently used shader programs; and

evict the least recently used shader program from the on-chip shader program instruction memory.

42. The computer-readable storage medium of claim 38, wherein the instructions that cause the one or more processors to evict the shader program from the on-chip shader program instruction memory comprise instructions that cause the one or more processors to:

overwrite at least a portion of the evicted shader program with at least a portion of the shader program to be loaded into the on-chip shader program instruction memory.