SHARING LOCAL CONTROL LINES ACROSS MULTIPLE PLANES IN A MEMORY DEVICE

• US 20130170299A1
• Filed: 12/29/2011
• Published: 07/04/2013
• Est. Priority Date: 12/29/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yip, Aaron
• Granted Patent: US 8,947,934 B2
• Time in Patent Office: Days
• US Class Current: 365/185.13
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Memory devices, methods for accessing a memory cell, and memory systems are disclosed. One such memory device includes a plurality of planes of memory cells. Each plane of memory cells includes series strings of memory cells that each have a select gate drain transistor. Control gates of corresponding select gates are coupled together by a shared local control line. Each of a plurality of global control lines are coupled to their corresponding local control line with only a single global select gate.

Claims

1. A memory device comprising:

a plurality of planes of memory cells, each plane having at least one series string of memory cells, each series string of memory cells having a local select gate wherein a control gate of each corresponding local select gate of the plurality of planes of memory cells is coupled to a local shared control line and only one global select gate is configured to control access for the local shared control line to a global control line.

2. The memory device of claim 1 wherein the local shared control line is a local select gate line and the global control line is a global select gate line.

3. The memory device of claim 1 wherein each plane comprises a plurality of series strings of memory cells.

4. The memory device of claim 1 wherein the plurality of planes of memory cells comprise a block of memory cells.

5. The memory device of claim 4 wherein each local select gate is a select gate drain transistor that couples its respective series string of memory cells to a data line.

6. The memory device of claim 5 wherein the data line is common only to the series strings in the block of memory cells.

7. A memory device comprising:

a first vertical plane of memory cells, wherein the first vertical plane of memory cells comprises a first vertical string of memory cells coupled to a first select gate; and

a second vertical plane of memory cells, wherein the second vertical plane of memory cells comprises a second vertical string of memory cells coupled to a second select gate,

wherein the first and second select gates are coupled to a shared local control line and only one global select gate couples the shared local control line to a global control line.

8. The memory device of claim 7 and further comprising:

a third vertical plane of memory cells, wherein the third vertical plane of memory cells comprises a third vertical string of memory cells coupled to a third select gate,

wherein the third select gate is coupled to the local shared control line and the third vertical plane does not include a global select gate that couples the third select gate to the global control line.

9. The memory device of claim 7 and further comprising control gates of each row of memory cells coupled to a local select line.

10. The memory device of claim 9 wherein each corresponding row of memory cells in each plane is coupled to the same local select line.

11. The memory device of claim 7 wherein the array of memory cells comprises one of a NAND architecture, a NOR architecture, or an AND architecture.

12. The memory device of claim 7 and further comprising:

a third vertical plane of memory cells, wherein the third vertical plane of memory cells comprises a third vertical string of memory cells coupled to a third select gate,

wherein the third select gate is not coupled to the shared local control line.

13. A method for accessing a select memory cell comprising:

activating a select gate to couple a global control line to an associated local control line that is shared by a plurality of local select gates across a plurality of planes of memory cells, wherein the selected memory cell is one of the plurality of planes; and

biasing an access line coupled to a control gate of the selected memory cell.

14. The method of claim 13 wherein activating the select gate activates each of the local select gates that share the associated local control line.

15. The method of claim 13 and further comprising biasing a data line coupled to the memory cell through one of the plurality of local select gates that share the local control line.

16. The method of claim 15 wherein the data line is biased with a voltage appropriate to an operation performed on the selected memory cell.

17. A system comprising:

a controller configured to control the memory system; and

a memory device coupled to the controller the memory device comprising;

a plurality of vertical planes of memory cells, each plane having at least one series string of memory cells, each series string of memory cells having a local select gate wherein a control gate of each corresponding local select gate of the plurality of planes of memory cells is coupled to a local shared control line and only one global select gate is configured to control access for the local shared control line to a global control line.

18. The system of claim 17 wherein the memory device further comprises control circuitry configured to activate the global select gate that is coupled between the control line and the global control line.

19. The system of claim 17 wherein the local shared control line is coupled only to control gates of select gates of a subset of the plurality of vertical planes of memory cells that is less than the plurality of vertical planes.

20. The system of claim 19 wherein the subset of the plurality of vertical planes comprise adjacent planes.

21. A system comprising:

a controller configured to control the system; and

a memory device coupled to the controller the memory device comprising;

a first vertical plane of memory cells, wherein the first vertical plane of memory cells comprises a first vertical string of memory cells coupled to a first select gate; and

a second vertical plane of memory cells, wherein the second vertical plane of memory cells comprises a second vertical string of memory cells coupled to a second select gate,

wherein the first and second select gates are coupled to a first shared local control line and only a first global select gate couples the first shared local control line to a first global control line.

22. The system of claim 21 and further comprising:

a third vertical plane of memory cells, wherein the third vertical plane of memory cells comprises a third vertical string of memory cells coupled to a third select gate; and

a fourth vertical plane of memory cells, wherein the fourth vertical plane of memory cells comprises a fourth vertical string of memory cells coupled to a fourth select gate,

wherein the third and fourth select gates are coupled to a second shared local control line and only a second global select gate couples the second shared local control line to a second global control line.

23. The system of claim 22 wherein the memory device further comprises memory control circuitry configured to control access to a selected memory cell of a select series string by controlling activation of one of the first or the second global select gates.

24. The system of claim 23 wherein the control circuitry is further configured to control a bias of a select line coupled to a control gate of the selected memory cell in order to access the selected memory cell.

25. The system of claim 23 wherein the memory control circuitry comprises a memory controller, address circuitry, a row decoder, a column decoder, I/O circuitry, write circuitry, and sense circuitry/page buffers.

26. The system of claim 22 wherein the first and second select gates are corresponding select gates.

27. The system of claim 26 wherein the third and fourth select gates are not corresponding select gates to the first and second select gates.

28. A memory device comprising:

a plurality of vertical planes of memory cells, each plane having a plurality of vertical strings of memory cells, each vertical string coupled to a respective local select gate, control gates of each of the corresponding local select gates of each plane coupled to a corresponding local control line wherein each corresponding local control line is coupled to a corresponding global control line only through one corresponding global select gate.

29. The memory device of claim 28 wherein the local select gates are select gate drain transistors.

30. The memory device of claim 29 wherein local select gates selectively couple their respective vertical string to a data line.

31. The memory device of claim 30 wherein the data line is a common bit line to a block of memory cells.