Method and system for counting data packets

• US 20130170368A1
• Filed: 12/07/2010
• Published: 07/04/2013
• Est. Priority Date: 06/04/2010
• Status: Active Grant

• Current Assignee: ZTE Corporation
• Original Assignee: ZTE Corporation
• Inventors: Yang, Jinmei
• Granted Patent: US 9,531,616 B2
• Time in Patent Office: Days
• US Class Current: 370/252
• CPC Class Codes: H04L 43/0876 Network utilisation, e.g. volume of load or congestion level
• CPC Class Codes: H04L 43/0888 Throughput

Abstract

The disclosure provides a method for counting data packets, which includes the following steps: counting packet pulse signals when a low bit counter is in a count state, and sending a carry signal when the low bit counter is full; and acquiring data from an address of a Random Access Memory (RAM) corresponding to the low bit counter which sends the carry signal, adding 1 to the acquired data and then writing the added data into the address. The disclosure also provides a system for counting data packets. According to the technical scheme of the disclosure, the occupancy rate of logical resources is reduced while the counting of the data packets in a network is finished at a high speed.

Claims

1. A method for counting data packets, comprising:

counting packet pulse signals when a low bit counter is in a count state, and sending a carry signal when the low bit counter is full; and

acquiring data from an address of a Random Access Memory (RAM) corresponding to the low bit counter which sends the carry signal, adding 1 to the acquired data and then writing the added data into the address.

2. The method according to claim 1, further comprising:

before counting packet pulse signals when a low bit counter is in a count state,

generating the packet pulse signals according to data packets.

3. The method according to claim 2, wherein the generating the packet pulse signals according to data packets comprises:

receiving, a data channel interface, the data packets transmitted by a data instrument which is connected with the data channel interface, generating various packet pulse signals according to the number of the channel and the type of the data packets, and sending the packet pulse signals to the channel.

4. The method according to claim 1, further comprising:

resetting data of the low bit counter when the low bit counter is in a reset state;

calculating the addresses of the RAMs corresponding to all low bit counters in the channel, and resetting the data in the addresses.

5. The method according to claim 4, wherein the resetting data of the low bit counter when the low bit counter is in a reset state, calculating the addresses of the RAMs corresponding to all low bit counters in the channel and resetting the data in the addresses comprises:

setting, by the low bit counter, the data of the low bit counter itself to be 0 when the low bit counter is in the reset state;

when polling in a polling mode to a channel in which a low bit counter is in the reset state, calculating the addresses of the RAMs corresponding to all low bit counters in the channel according to the number of the channel and the type of the data packets, and sending the addresses to a state machine;

setting, by the state machine, the data in the addresses to be 0.

6. The method according to claim 1, further comprising:

before acquiring data from an address of an RAM corresponding to the low bit counter which sends the carry signal, adding 1 to the acquired data and then writing the added data into the address,

when polling in a polling mode to a channel in which the low bit counter providing the carry signal is located, calculating the address of the RAM corresponding to the low bit counter according to the number of the channel and the type of the data packets, and forwarding the calculated RAM address to a state machine.

7. The method according to claim 1, wherein the counting packet pulse signals when a low bit counter is in a count state, and sending a carry signal when the low bit counter is full comprises:

each low bit counter in the channel identifying the packet pulse signals counted by itself according to a packet header and counting the packet pulse signals of itself, and sending the carry signal used for sending a carry request when the low bit counter is full.

8. The method according to claim 1, wherein the acquiring data from the address of the RAM corresponding to the low bit counter which sends the carry signal, and adding 1 to the data and then writing the data into the address comprises:

after receiving the address of the RAM, sending, by a state machine, a write enabling pulse signal to the RAM;

when a rising edge of a next clock comes, outputting, by the RAM, the data stored in the address of the RAM itself to the state machine;

adding, the state machine, 1 to the data and then sending the added data to the RAM to store;

after finishing the carry work, resetting, by the state machine, the state of the state machine itself to be a read and write RAM complete state.

9. The method according to claim 1, further comprising:

after adding 1 to the data and then writing the added data into the address,

clearing a carry signal of the low bit counter.

10. The method according to claim 9, wherein the clearing a carry signal of the low bit counter comprises:

after resetting its state to be a read and write RAM complete state, triggering, by the state machine, a carry clear module to start working;

generating, by the carry clear module, a carry clear pulse according to the number of the channel and the type of the data packet corresponding to the low bit counter which sends the carry signal, and sending the carry clear pulse to the state machine;

clearing, by the state machine, the carry signal of the low bit counter which generates the carry signal.

14. The method according to claim 2, wherein the acquiring data from the address of the RAM corresponding to the low bit counter which sends the carry signal, and adding 1 to the data and then writing the data into the address comprises:

after receiving the address of the RAM, sending, by a state machine, a write enabling pulse signal to the RAM;

when a rising edge of a next clock comes, outputting, by the RAM, the data stored in the address of the RAM itself to the state machine;

adding, the state machine, 1 to the data and then sending the added data to the RAM to store;

after finishing the carry work, resetting, by the state machine, the state of the state machine itself to be a read and write RAM complete state.

15. The method according to claim 3, wherein the acquiring data from the address of the RAM corresponding to the low bit counter which sends the carry signal, and adding 1 to the data and then writing the data into the address comprises:

after receiving the address of the RAM, sending, by a state machine, a write enabling pulse signal to the RAM;

when a rising edge of a next clock comes, outputting, by the RAM, the data stored in the address of the RAM itself to the state machine;

adding, the state machine, 1 to the data and then sending the added data to the RAM to store;

after finishing the carry work, resetting, by the state machine, the state of the state machine itself to be a read and write RAM complete state.

16. The method according to claim 4, wherein the acquiring data from the address of the RAM corresponding to the low bit counter which sends the carry signal, and adding 1 to the data and then writing the data into the address comprises:

after receiving the address of the RAM, sending, by a state machine, a write enabling pulse signal to the RAM;

when a rising edge of a next clock comes, outputting, by the RAM, the data stored in the address of the RAM itself to the state machine;

adding, the state machine, 1 to the data and then sending the added data to the RAM to store;

after finishing the carry work, resetting, by the state machine, the state of the state machine itself to be a read and write RAM complete state.

17. The method according to claim 5, wherein the acquiring data from the address of the RAM corresponding to the low bit counter which sends the carry signal, and adding 1 to the data and then writing the data into the address comprises:

after receiving the address of the RAM, sending, by a state machine, a write enabling pulse signal to the RAM;

when a rising edge of a next clock comes, outputting, by the RAM, the data stored in the address of the RAM itself to the state machine;

adding, the state machine, 1 to the data and then sending the added data to the RAM to store;

after finishing the carry work, resetting, by the state machine, the state of the state machine itself to be a read and write RAM complete state.

18. The method according to claim 6, wherein the acquiring data from the address of the RAM corresponding to the low bit counter which sends the carry signal, and adding 1 to the data and then writing the data into the address comprises:

after receiving the address of the RAM, sending, by a state machine, a write enabling pulse signal to the RAM;

when a rising edge of a next clock comes, outputting, by the RAM, the data stored in the address of the RAM itself to the state machine;

adding, the state machine, 1 to the data and then sending the added data to the RAM to store;

after finishing the carry work, resetting, by the state machine, the state of the state machine itself to be a read and write RAM complete state.

19. The method according to claim 7, wherein the acquiring data from the address of the RAM corresponding to the low bit counter which sends the carry signal, and adding 1 to the data and then writing the data into the address comprises:

after receiving the address of the RAM, sending, by a state machine, a write enabling pulse signal to the RAM;

when a rising edge of a next clock comes, outputting, by the RAM, the data stored in the address of the RAM itself to the state machine;

adding, the state machine, 1 to the data and then sending the added data to the RAM to store;

after finishing the carry work, resetting, by the state machine, the state of the state machine itself to be a read and write RAM complete state.

20. The method according to claim 2, further comprising:

after adding 1 to the data and then writing the added data into the address,

clearing a carry signal of the low bit counter.

11. A system for counting data packets, comprising:

a low bit counter, a state machine and a Random Access Memory (RAM), wherein

the low bit counter is configured to count packet pulse signals when the low bit counter itself is in a count state and to send a carry signal when the low bit counter itself is full;

the state machine is configured to acquire data from an address of the RAM corresponding to the low bit counter which sends the carry signal, to add 1 to the acquired data and then to write the added data into the address; and

the RAM is configured to provide the data of itself to the state machine and to store the data written by the state machine.

12. The system according to claim 11, further comprising at least one of a data channel interface, a polling algorithm module and a carry clear module;

wherein

the data channel interface is configured to generate the packet pulse signals according to data packets;

the polling algorithm module is configured to poll channels, to trigger an address arithmetic module when polling to a channel in which the low bit counter is in a reset state or provides a carry signal;

wherein the address arithmetic module is configured to calculate, when triggered by the polling algorithm module, the address of the RAM corresponding to the low bit counter according to the number of the channel and the type of the data packets and to send the address to the state machine;

the carry clear module is configured to generate, when triggered by the state machine, a carry clear pulse according to the number of the channel and the type of the data packet corresponding to the low bit counter which sends the carry signal, and to send the carry clear pulse to the state machine.

13. The system according to claim 11, wherein

the low bit counter is further configured to reset data of itself when being in a reset state;

and

the state machine is further configured to reset the data in the address of the RAM is sent from the address arithmetic module.