PERFORMANCE OF A POWER CONSTRAINED PROCESSOR

• US 20130173933A1
• Filed: 12/29/2011
• Published: 07/04/2013
• Est. Priority Date: 12/29/2011
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ramani, Karthik, Brothers, John W., Presant, Stephen
• Application Number:
  US13/340,032
• Publication Number:
  US 20130173933A1
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Provided is a method for improving performance of a processor. The method includes computing utilization values of components within the processor and determining a maximum utilization value based upon the computed utilization values. The method also includes comparing (i) the maximum utilization value with a first threshold and (ii) differences between the computed utilization values and a second threshold.

Claims

1. A method for improving performance of a processor, comprising:

computing utilization values of components within the processor;

determining a maximum utilization value based upon the computed utilization values; and

comparing (i) the maximum utilization value with a first threshold and (ii) differences between the computed utilization values and a second threshold.

2. The method of claim 1, further comprising modifying utilization values of the components using control variables.

3. The method of claim 2, wherein the control variable is frequency.

4. The method of claim 2, wherein each component includes an independently controlled voltage rail.

5. The method of claim 2, further comprising throttling throughput to address throughput limitations caused by components outside of the processor.

6. The method of claim 5, where in the throughput limitation is caused by a central processing unit (CPU) or memory.

7. The method of claim 1, further comprising increasing frequency of high utilization components based on available power slack.

8. A system, comprising:

a memory device; and

a processing unit coupled to the memory device and configured to;

compute utilization values of components within the processing unit;

determine a maximum utilization value based upon the computed utilization values; and

compare (i) the maximum utilization value with a first threshold (ii) differences between the computed utilization values with a second threshold.

9. The system of claim 8, further comprising modifying utilization values of the components using control variables.

10. The system of claim 8, wherein each component has independently controlled voltage rail.

11. The system of claim 8, wherein frequency of a component is increased to improve performance of the processor.

12. A non-transitory computer readable medium having instructions recorded thereon that, when executed by a computing device, cause the computing device to perform a method to manage performance of a processor including a plurality of components, comprising:

computing utilization values of components in the processor;

determining a maximum utilization value based upon the computed utilization values; and

comparing (i) the maximum utilization value with a first threshold and (ii) differences between the computed utilization values and a second threshold.

13. The computer readable media of claim 12, further comprising:

modifying utilization values of the components using control variables.

14. The computer readable media of claim 13, wherein each component has independently controlled voltage rail.