Facilitating Error Detection And Recovery In A Memory System

• US 20130173991A1
• Filed: 10/06/2011
• Published: 07/04/2013
• Est. Priority Date: 10/12/2010
• Status: Abandoned Application

• Current Assignee: Frederick A. Ware, Leibowitz, Brian S.
• Original Assignee: Frederick A. Ware, Leibowitz, Brian S.
• Inventors: Ware, Frederick A., Leibowitz, Brian S.
• Application Number:
  US13/820,963
• Publication Number:
  US 20130173991A1
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 2213/0038 System on Chip
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

The disclosed embodiments relate to a system for accessing a data word in a memory. During operation, the system receives a request to access a data word, wherein the request includes a physical address for the data word. Next, the system translates the physical address into a mapped address, wherein the translation process spreads out the data words and intersperses groups of consecutive error information between groups of consecutive data words. Finally, the system uses the mapped address to access the data word and corresponding error information for the data word from the memory.

Claims

1. A memory controller, comprising:

a circuit to generate

a first address identifying a first memory array to store first data, and

a second address identifying a second memory array to store second data; and

an interface to provide

for storage in the first memory array, the first data and error information associated with second data, and

for storage in the second memory array, the second data and error information associated with first data.

2. The memory controller of claim 1, wherein the memory controller is configured to access a first data word from the first memory array in parallel with accessing error information for the first data word from the second memory array.

3. The memory controller of claim 1, wherein the memory controller further comprises circuitry for generating and checking the error information.

4. The memory controller of claim 1, wherein:

the memory controller is configured to store unprotected data words without error information;

data words with error information are stored in a first region of memory; and

the unprotected data words without error information are stored in a second region of memory.

14. The memory controller of claim 1, wherein:

the memory controller further comprises an address-translation circuit that translates a physical address for a memory reference into a mapped address; and

the translation process intersperses consecutive data words with consecutive EDC syndromes, so that data words in the first data are associated with corresponding EDC syndromes in the second data, and data words in the second data are associated with corresponding EDC syndromes in the first data.

5-13. -13. (canceled)

15. (canceled)

16. A method of operation of a memory controller, the method comprising:

generating a first address that identifies a first memory array to store first data;

generating a second address that identifies a second memory array to store second data;

outputting the first data and error information associated with second data, for storage in the first memory array; and

outputting the second data and error information associated with first data, for storage in the second memory array.

17. The method of claim 16, wherein the method further comprises using the first address to access a first data word from the first memory array in parallel with using the second address to access error information for the first data word from the second memory array.

21. The method of claim 16, wherein:

the first memory array and the second memory array comprise different bank groups;

the first memory array is located in a first memory device; and

the second memory array is located in a second memory device.

22. The method of claim 16, wherein the first memory array and the second memory array comprise different bank groups which are located in the same memory device.

23. The method of claim 16, wherein the first memory array and the second memory array are associated with different columns in a memory device, so that a given row in the memory device includes bits associated with the first memory array and bits associated with the second memory array.

18-20. -20. (canceled)

24. (canceled)

25. A method of operation of a memory controller, the method comprising:

generating a command to access data from a memory device coupled to the memory controller, the memory device having first and second storage arrays;

transmitting to the memory device, a first address that identifies a storage location within the first storage array for the data; and

transmitting to the memory device, a second address that identifies a second storage location within the second storage array for error information associated with the data.

26. The method of claim 25, wherein:

error information for a first data word located in the first memory array is stored in the second memory array; and

error information for a second data word located in the second memory array is stored in the first memory array.

27. The method of claim 25, wherein:

a given data word includes 64 bits of data; and

the error information for the given data word includes an 8-bit EDC syndrome for the given data word.

28. The method of claim 27, wherein groups of consecutive EDC syndromes are interspersed between groups of consecutive data words.

29. The method of claim 25, wherein a given data word is accessed in parallel with the error information for the given data word.

30-33. -33. (canceled)

34. A memory device, comprising:

at least a first and a second storage array;

a command interface to receive a command to write data to a first storage location within the first storage array;

a first interface to receive data associated with the command; and

a second interface to receive error information associated with the data, wherein the error information is stored in the second storage array.

35. The memory device of claim 34, wherein:

the set of storage locations is organized into multiple independently accessible memory arrays, including a first memory array and a second memory array; and

the memory device is to store data words along with associated error information for the data words so that

error information for a first data word located in the first memory array is stored in the second memory array, and

error information for a second data word located in the second memory array is stored in the first memory array.

36. The memory device of claim 34, wherein the memory device further comprises circuitry for generating and checking the error information.

37. The memory device of claim 34, wherein the memory device is to:

simultaneously receive a first read access request directed to the first data word in the first memory array and a second read access request directed to the error information for the first data word in the second memory array; and

in response to the first and second read access requests, read out the first data word from the first memory array in parallel with reading out the error information for the first data word from the second memory array.

38. The memory device of claim 34, wherein the memory device is to:

simultaneously receive a first write access request directed to the location of the first data word in the first memory array and a second write access request directed to the location of the error information for the first data word in the second memory array; and

in response to the first and second write access requests, write a new data word to the location of the first data word in the first memory array in parallel with writing new error information for the new data word to the location of the error information for the first data word in the second memory array.

50. The memory device of claim 34, wherein

the memory device includes

a first set of memory banks, and

a second set of memory banks;

the first and second sets of memory banks are oriented on the memory device so that data (DQ) lines and command/address (CA) lines are coupled to the first and second sets of memory banks through signal lines which run along one side of the memory device.

51. The memory device of claim 34, wherein:

the memory device includes

a first set of memory banks, and

a second set of memory banks;

the first and second sets of memory banks are oriented on the memory device so that data (DQ) lines and command/address (CA) lines are coupled to the first and second sets of memory banks through signal lines located between the first and second sets of memory banks.

39-49. -49. (canceled)

52-61. -61. (canceled)