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Facilitating Error Detection And Recovery In A Memory System

  • US 20130173991A1
  • Filed: 10/06/2011
  • Published: 07/04/2013
  • Est. Priority Date: 10/12/2010
  • Status: Abandoned Application
First Claim
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1. A memory controller, comprising:

  • a circuit to generatea first address identifying a first memory array to store first data, anda second address identifying a second memory array to store second data; and

    an interface to providefor storage in the first memory array, the first data and error information associated with second data, andfor storage in the second memory array, the second data and error information associated with first data.

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