Low Latency Virtual Machine Page Table Management
First Claim
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1. A processor, comprising:
- instruction hardware to receive a view switch instruction; and
execution hardware to execute a view switch instruction.
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Abstract
Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claimed.
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Citations
3 Claims
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1. A processor, comprising:
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instruction hardware to receive a view switch instruction; and execution hardware to execute a view switch instruction.
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2. A method, comprising:
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receiving, by a processor, a view switch instruction; and executing, by a processor, a view switch instruction.
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3. A system, comprising:
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memory; and a processor including instruction hardware to receive a view switch instruction, and execution hardware to execute a view switch instruction.
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Specification