Semiconductor-Based Device Authentication

• US 20130176104A1
• Filed: 01/09/2012
• Published: 07/11/2013
• Est. Priority Date: 01/09/2012
• Status: Active Grant

• Current Assignee: Malikie Innovations Limited (Key Patent Innovations Limited)
• Original Assignee: Blackberry Limited
• Inventors: RICH, David Gerard, Feng, Yu William
• Granted Patent: US 8,793,810 B2
• Time in Patent Office: Days
• US Class Current: 340/5.8
• CPC Class Codes: H04W 12/06 Authentication

Abstract

Various embodiments of devices and associated methods are described herein for authenticating electrical devices. In one aspect, an electrical device is provided comprising an interface configured to receive and transmit signals; a power line coupled to the interface and configured to provide a power signal thereto; and an authentication circuit coupled to the interface and the power line. The authentication circuit is configured to disable the power signal on the power line for a specified time period in response to an authentication request signal received at the interface and to provide an authentication response signal on the power line to represent the disabling of the power signal.

Claims

1. An electrical device comprising:

an interface configured to receive and transmit signals;

a power line coupled to the interface and configured to provide a power signal thereto; and

an authentication circuit coupled to the interface and the power line, the authentication circuit being configured to disable the power signal on the power line for a specified time period in response to an authentication request signal received at the interface and to provide an authentication response signal on the power line to represent the disabling of the power signal.

2. The electrical device of claim 1, wherein the power signal is provided by an external power source.

3. The electrical device of claim 1, wherein the electrical device comprises at least one battery cell configured to generate the power signal.

4. The electrical device of claim 3, wherein the authentication circuit comprises:

a battery-protection Integrated Circuit (IC) coupled to the at least one battery cell and the interface, the battery-protection IC configured to receive the authentication request signal; and

a discharge transistor coupled to the battery-protection IC and the at least one battery cell,

wherein the battery-protection IC is configured to turn off the discharge transistor to disconnect the at least one battery cell for the specified time period in response to the authentication request signal.

5. The electrical device of claim 3, wherein the authentication circuit comprises:

a battery-protection Integrated Circuit (IC) coupled to the at least one battery cell and the interface;

a multiplexer coupled to the battery-protection IC and the interface, the multiplexer being configured to receive the authentication request signal; and

a discharge transistor coupled to the battery-protection IC and the at least one battery cell,

wherein the discharge transistor is configured to turn off in response to the authentication request signal in order to disconnect the at least one battery cell for the specified time period.

6. The electrical device of claim 5, further comprising a cryptographic IC configured to generate a cryptographic response when provided with the authentication request signal.

7. The electrical device of claim 3, wherein the authentication circuit comprises a battery-protection Integrated Circuit (IC) coupled to the at least one battery cell and the interface and a discharge transistor coupled to the battery-protection IC and the at least one battery cell, and, in response to the authentication request signal, the battery-protection IC is configured to generate a cryptographic response as the authentication response signal in a first mode of operation, and the battery-protection IC is configured to turn off the discharge transistor to disconnect the at least one battery cell for the specified time period to provide the authentication response signal in a second mode of operation.

8. An authentication device for authenticating a test device that provides a power signal, the authentication device comprising:

an interface to couple the authentication device with the test device and allow signals to be transferred therebetween;

a memory for storing at least one expected authentication response; and

a processor coupled to the interface, the processor being configured to control operation of the authentication device, to generate and send an authentication request signal to the test device via the interface, and to compare an authentication response signal received from the test device via the interface in response to the authentication request signal with an expected authentication response in order to authenticate the test device, the expected authentication response representing a disabling of the power signal by the test device.

9. The authentication device of claim 8, further comprising an authentication indicator to indicate authentication results for the test device.

10. The authentication device of claim 8, wherein the memory further comprises at least one cryptographic challenge and corresponding expected cryptographic response, and the processor is configured to send the at least one cryptographic challenge to the test device via the interface, and to compare a resulting cryptographic response from the test device with the expected cryptographic response stored in the memory in order to authenticate the test device.

11. The authentication device of claim 8, wherein the processor is configured to perform a two-stage authentication test by testing if the test device can disable the power signal in response to the authentication request signal and testing if the test device can provide a correct cryptographic response in response to at least one cryptographic challenge.

12. A method of authenticating an electrical device, wherein the method comprises:

enabling a power signal on a power line at an interface of the electrical device;

receiving an authentication request signal at the interface;

disabling the power signal on the power line for a specified time period in response to the authentication request signal; and

providing an authentication response signal on the power line to represent the disabling of the power signal.

13. The method of claim 12, wherein the method further comprises:

receiving the authentication request signal at a battery-protection Integrated Circuit (IC) coupled to the power line and the interface; and

turning off a discharge transistor coupled to the battery-protection IC and the power line in response to the authentication request signal to disable the power signal on the power line for the specified time period.

14. The method of claim 12, wherein the method further comprises:

receiving the authentication request signal at a multiplexer coupled to a battery-protection IC and the interface; and

turning off a discharge transistor coupled to the battery-protection IC and the power line in response to the authentication request signal to disable the power signal on the power line for the specified time period.

15. The method of claim 12, further comprising using a cryptographic Integrated Circuit to generate a cryptographic response when provided with a cryptographic challenge.

16. The method of claim 12, wherein the method further comprises operating a battery-protection Integrated Circuit (IC) coupled to the power line and the interface in first and second modes in response to the authentication request signal, wherein in the first mode the battery-protection IC is configured to generate a cryptographic response as the authentication response signal, and in the second mode the battery-protection IC is configured to turn off a discharge transistor to disable the power line for the specified time period to provide the authentication response signal.

17. A method of using an authentication device to authenticate a test device that provides a power signal, the method comprising:

storing at least one expected authentication response in a memory of the authentication device;

sending an authentication request signal to the test device;

comparing an authentication response signal received from the test device in response to the authentication request signal with the expected authentication response representing a disabling of the power signal by the test device; and

authenticating the test device if the authentication response signal is similar to the expected authentication response.

18. The method of claim 17, further comprising performing a two-stage authentication test by testing if the test device can disable the power signal in response to the authentication request signal and testing if the test device can provide a correct cryptographic response in response to at least one cryptographic challenge.

19. A computer readable medium comprising a plurality of instructions executable on a microprocessor of an electrical device for adapting the microprocessor to implement a method of authenticating the electrical device, wherein the method comprises:

enabling a power signal on a power line of the electrical device;

receiving an authentication response signal;

disabling the power signal on the power line for a specified time period in response to the authentication request signal; and

providing an authentication response signal on the power line to represent the disabling of the power signal.

20. A computer readable medium comprising a plurality of instructions executable on a microprocessor of an electrical device for adapting the microprocessor to implement a method of authenticating a test device, wherein the method comprises:

sending an authentication request signal to the test device;

comparing an authentication response signal received from the test device in response to the authentication request signal with an expected authentication response representing a disabling of a power signal of the test device; and

authenticating the test device if the authentication request signal is similar to the expected authentication response.