Thermally-Insulated Micro-Fabricated Atomic Clock Structure and Method of Forming the Atomic Clock Structure

• US 20130176703A1
• Filed: 01/07/2012
• Published: 07/11/2013
• Est. Priority Date: 01/07/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hopper, Peter J., French, William, Mawson, Paul, Hunt, Steven, Parsa, Roozbeh, Fallon, Martin, Gabrys, Ann, Papou, Andrei
• Granted Patent: US 9,024,397 B2
• Time in Patent Office: Days
• US Class Current: 361/820
• CPC Class Codes: G04F 5/14 using atomic clocks
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 31/00 Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof H10K30/00 takes precedence; devices consisting of a plurality of solid state components formed in, or on, a common substrate, other than combinations of radiation-sensitive components with one or more electric light sources, H01L27/00
• CPC Class Codes: H01L 31/022408 for devices characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/024 Arrangements for cooling, heating, ventilating or temperature compensation for photovoltaic devices H01L31/052
• CPC Class Codes: H01L 31/103 the potential barrier being of the PN homojunction type
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: H03L 7/26 using energy levels of molecules, atoms, or subatomic particles as a frequency reference
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells

Abstract

A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to −40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.

Claims

1. A semiconductor structure comprising:

a photodiode structure including;

a substrate having a conductivity type, a device surface, a non-device surface, and a thermal barrier opening that extends into the substrate from the non-device surface;

a number of circuit elements that lie within the substrate; and

a metal interconnect structure that touches the substrate, the metal interconnect structure making electrical connections to the number of circuit elements to realize a photodiode circuit.

2. The semiconductor structure of claim 1 wherein the thermal barrier opening exposes the metal interconnect structure.

3. The semiconductor structure of claim 1 wherein the thermal barrier opening horizontally surrounds the number of circuit elements.

4. The semiconductor structure of claim 1 and further comprising a package electrically connected to the metal interconnect structure, the substrate lying within the package, an air pressure within the thermal barrier opening being less than an atmospheric pressure outside of the package.

5. The semiconductor structure of claim 1 wherein the metal interconnect structure further includes:

a first non-conductive layer that touches the device surface of the substrate;

a plurality of contacts that extend through the first non-conductive layer to make electrical connections to the number of circuit elements;

a plurality of metal-1 traces that touch the first non-conductive layer and the plurality of contacts;

a second non-conductive layer that touches the first non-conductive layer and the plurality of metal-1 traces;

a plurality of vias that extend through the second non-conductive layer to make electrical connections to the number of metal-1 traces; and

a plurality of metal-2 traces that touch the second non-conductive layer and the plurality of vias, the plurality of metal-2 traces having a thermal conductivity that is greater than a thermal conductivity of the metal-1 traces.

6. The semiconductor structure of claim 5 wherein the photodiode structure further includes a peripheral opening that extends through the substrate and the first non-conductive layer to expose bond pad regions of the metal-1 traces.

7. The semiconductor structure of claim 1 wherein the photodiode structure further includes:

a metal plate that touches the non-device surface of the substrate; and

a metal trace that touches the non-device surface of the substrate, the metal trace being spaced apart from the metal plate and horizontally surrounding the metal plate.

8. The semiconductor structure of claim 7 wherein the photodiode structure further includes a metal cover that touches the metal plate and the substrate, the metal cover extending into the thermal barrier opening, and being spaced apart from the metal interconnect structure.

9. The semiconductor structure of claim 2 and further comprising a vapor cell structure that touches the metal interconnect structure, the vapor cell structure having a vapor cell opening and a thermal barrier opening that both extend completely through the vapor cell structure, the thermal barrier opening in the vapor cell structure horizontally surrounding the vapor cell opening, the metal interconnect structure fully closing one end of the vapor cell opening and one end of the thermal barrier opening in the vapor cell structure.

10. The semiconductor structure of claim 9 and further comprising a lid structure that touches the vapor cell structure to close and hermetically seal the vapor cell opening to form a vapor cell, the lid structure having an access opening that extends completely through the lid structure to expose the thermal barrier opening in the vapor cell structure.

11. The semiconductor structure of claim 10 and further comprising a package electrically connected to the metal interconnect structure, the substrate lying within the package, an air pressure within the thermal barrier opening in the vapor cell structure and the access opening being less than an atmospheric pressure outside of the package.

12. The semiconductor structure of claim 10 wherein the vapor cell has a gas region, a channel region, and a deposition region, the channel region having a width that prevents an aqueous solution from flowing between the gas region and the deposition region.

13. The semiconductor structure of claim 10 and further comprising a gas contained within the vapor cell.

14. The semiconductor structure of claim 13 and further comprising:

an optics structure attached to the lid structure, the optics structure having an access opening that extends completely through the optics structure to expose the access opening in the lid structure and the thermal barrier opening in the vapor cell structure; and

an optics package attached to the optics structure, the optics package including a quarter wave plate circular polarizer.

15. A semiconductor device comprising:

a package having a metal lead frame, the metal lead frame having a die attach pad;

a substrate structure having;

a substrate having an interconnect surface and a non-interconnect surface;

a metal layer that touches the non-interconnect surface of the substrate;

a plurality pillars that touch the metal layer, the plurality of pillars being non-conductive and spaced apart;

a lattice structure that touches the plurality of pillars and the die attach pad, the lattice structure being non-conductive; and

a metal interconnect structure that touches the interconnect structure of the substrate; and

a vertical cavity surface emitting laser (VCSEL) attached to the metal interconnect structure, the VCSEL outputting laser light.

16. The semiconductor device of claim 15 wherein the metal interconnect structure further includes:

a first non-conductive layer that touches the interconnect surface of the substrate;

a plurality of metal-1 traces that touch the first non-conductive layer;

a second non-conductive layer that touches the first non-conductive layer and the plurality of metal-1 traces;

a plurality of vias that extend through the second non-conductive layer to make electrical connections to the number of metal-1 traces; and

a plurality of metal-2 traces that touch the second non-conductive layer and the plurality of vias, the plurality of metal-2 traces having a thermal conductivity that is less than a thermal conductivity of the metal-1 traces.

17. The semiconductor device of claim 15 and further comprising a spacer structure attached to the metal interconnect structure, the spacer structure having an optical opening, the VCSEL lying within the optical opening.

18. The semiconductor device of claim 17 and further comprising:

an optical base structure attached to the spacer structure; and

an optics package attached to the optical base structure, the optics package including a quarter wave plate circular polarizer, and lying within the optical opening of spacer structure.

19. The semiconductor device of claim 18 wherein the optics package is spaced apart from the VCSEL.

20. A method of forming a semiconductor structure comprising:

forming a photodiode die including;

forming a substrate having a conductivity type, a device surface, and a non-device surface;

forming a number of circuit elements that lie within the substrate; and

forming a metal interconnect structure having;

a first non-conductive layer that touches the device surface of the substrate;

a plurality of contacts that extend through the first non-conductive layer to make electrical connections to the number of circuit elements;

a plurality of metal-1 traces that touch the first non-conductive layer and the plurality of contacts;

a second non-conductive layer that touches the first non-conductive layer and the plurality of metal-1 traces;

a plurality of vias that extend through the second non-conductive layer to make electrical connections to the number of metal-1 traces; and

a plurality of metal-2 traces that touch the second non-conductive layer and the plurality of vias, the plurality of metal-2 traces having a thermal conductivity that is greater than a thermal conductivity of the metal-1 traces.