ADJUSTING OPERATING PARAMETERS FOR MEMORY CELLS BASED ON WORDLINE ADDRESS AND CYCLE INFORMATION

• US 20130176784A1
• Filed: 02/22/2013
• Published: 07/11/2013
• Est. Priority Date: 03/30/2011
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: STEC Incorporated (Western Digital Corporation)
• Inventors: Ziperovich, Pablo Alejandro, Cometti, Aldo G.
• Granted Patent: US 9,047,955 B2
• Time in Patent Office: Days
• US Class Current: 365/185.11
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

Disclosed is an apparatus and method for adjusting operating parameters in a storage device. A controller in a solid state drive monitors current operating conditions for blocks of memory used to store data in the drive. When a block has been subjected to a predetermined number of program/erase cycles one or more stored bias values are retrieved from a storage location based on the wordline(s) associated with a current memory operation. The one or more parameters of the memory operation are then adjusted based on the one or more stored bias values, and the memory operation performed on the block of memory cells using the adjusted parameters.

Claims

1. A method for adjusting operating parameters in a storage device, comprising:

determining a current memory cycle condition associated with a block of memory cells in connection with a memory operation to be performed on the block of memory cells; and

on the current memory cycle condition satisfying a predetermined threshold;

retrieving, from a parameter storage location, one or more stored bias values for the memory operation based on one or more wordlines associated with the memory operation;

adjusting one or more parameters of the memory operation based on the one or more stored bias values; and

performing the memory operation on the block of memory cells using the adjusted parameters.

2. The method of claim 1, wherein the memory cycle condition is a current number of program/erase cycles, and wherein the predetermined threshold is a predetermined number of program/erase cycles.

3. The method of claim 2, wherein the memory operation is a program operation and the one or more parameters comprise a program verify level.

4. The method of claim 2, wherein the memory operation is a read operation and the one or more parameters comprise a read level.

5. The method of claim 1, further comprising:

determining a current error rate for one or more cells associated with the one or more wordlines;

determining a delta error rate by comparing the current error rate with a stored error rate for the current memory cycle condition and the one or more wordlines; and

adjusting the one or more stored bias values address based on the delta error rate.

6. The method of claim 5, wherein the one or more stored bias values are increased if the current error rate is greater than the stored error rate.

7. The method of claim 5, wherein the one or more stored bias values are set to a default value if the current error rate is lower than the stored error rate.

8. The method of claim 5, wherein adjusting the one or more stored bias values comprises setting the one or more stored bias values to a predetermined value.

9. The method of claim 1, wherein the one or more stored bias values offset a current shift in cell program levels associated with the one or more wordlines, and restore the cell program levels to within a predetermine tolerance of a predetermined value for the current memory cycle condition.

10. The method of claim 9, wherein the predetermined value for the current memory cycle condition comprises a minimum or maximum cell program level based on manufacturing data for a distribution of cell program levels.

11. The method of claim 1, wherein, for each wordline in a memory block, a plurality of bias values are stored for a plurality of respective memory cycle conditions, wherein a memory cycle condition is a program/erase cycle or a data retention time associated with the memory block.

12. The method of claim 11, wherein the parameter storage location is a lookup table configured to provide a bias value at runtime in response to an indexing of an address of a respective wordline and corresponding memory cycle condition.

13. A machine-readable medium including machine-executable instructions thereon that, when executed by a computer or machine, perform a method for adjusting operating parameters in a storage device, the method comprising:

performing, for one or more memory blocks, a predetermined number of program/erase cycles on memory cells associated with a wordline address;

retrieving one or more stored bias values from a lookup table based on the wordline address and the predetermined number of program/erase cycles;

adjusting one or more parameters of a memory operation based on the one or more stored bias values; and

performing the memory operation on the memory cells associated with the wordline address using the adjusted parameters.

14. The machine-readable medium of claim 13, wherein the predetermined number of program/erase cycles is a minimum threshold of a range of program/erase cycles for the one or more memory blocks, the bias values being retrieved for memory operations performed while a current number of program/erase cycles is within the range of program/erase cycles.

15. The machine-readable medium of claim 13, wherein the lookup table comprises bias values indexed by wordline address and a range of program/erase cycles.

16. The machine-readable medium of claim 13, wherein the one or more stored bias values offset a current shift in cell program levels associated with the wordline address, and restore the cell program levels to within a predetermine tolerance of a predetermined value for the predetermined number of program/erase cycles.

17. The machine-readable medium of claim 13, further comprising:

determining a current error rate for cells associated with the wordline address;

determining a difference between the current error rate with a stored error rate; and

modifying the one or more stored bias values based on the difference.

18. The machine-readable medium of claim 17, wherein the one or more stored bias values are modified if the difference satisfies a predetermined threshold.

19. The machine-readable medium of claim 18, wherein if the current error rate is greater than the stored error rate then the one or more stored bias values are increased, and if the current error rate is lower than the stored error rate then the one or more stored bias values are set to a predetermined value.

20. A system, comprising:

a processor;

one or more flash memory; and

one or more memory media having bias values stored thereon, the stored bias values corresponding to one or more wordline addresses of one or more memory blocks of the flash memory, the one or more memory media having instructions stored thereon that, when executed by the processor, cause the processor to;

perform a number of program/erase cycles on the block of memory;

determine a current error rate for one or more memory cells associated with the one or more wordline addresses;

generate a delta error rate by comparing the current error rate with a stored error rate for the one or more wordline addresses and the number of program/erase cycles;

modify, based on the delta error rate, a stored bias value corresponding to the one or more wordline addresses; and

adjust one or more operating parameters for a memory operation to be performed on the one or more memory cells based on the modified stored bias value.