PROCESSOR FOR SITUATIONAL ANALYSIS

• US 20130179389A1
• Filed: 07/13/2011
• Published: 07/11/2013
• Est. Priority Date: 07/13/2010
• Status: Active Grant

• Current Assignee: M8
• Original Assignee: M8
• Inventors: Malle, Jean-Pierre
• Granted Patent: US 9,349,097 B2
• Time in Patent Office: Days
• US Class Current: 706/47
• CPC Class Codes: G06F 16/283 Multi-dimensional databases or data warehouses, e.g. MOLAP or ROLAP
• CPC Class Codes: G06N 5/022 Knowledge engineering; Knowledge acquisition
• CPC Class Codes: G06N 5/04 Inference or reasoning models

Abstract

The present invention relates to a data-processing device, characterized in that it includes, in combination: a memory (10) which is organized into two spaces, one containing attributes describing the stored data, and the other containing connectivity links among the stored data, and which is organized according to one or more dimensions respectively associated with attributes and divided into one or more hierarchized segments, the data being informed by creating, deleting, or modifying attribute values characterizing said segments; a means (11) for integrating one or more incoming information streams, which analyzes said streams in order to determine the data constituting same and to structure said data and the attributes thereof according to the organization of said memory (10); an inference engine (14) implementing, in parallel or in series, inference rules (141) grouped together in libraries (15), said rules (141) being programmed to regenerate a sequence including at least one segment of the memory, by creating, deleting, or modifying at least one datum and/or at least one attribute value and/or at least one connectivity link during the implementation thereof in the at least one space of the memory; a means (13) for allocating resources activating or deactivating the inference rules (141) on the basis of a priority rule; a means (12) for extracting data, which are identified by programming and/or by at least one selected attribute value and/or at least one selected connectivity link, and/or which are located in one or more selected segments of the memory (10), and providing same in one or more outgoing information streams. The present invention also relates to an information-processing system and to an associated computer program product.

Claims

1. Data-processing device (1) characterized in that it comprises in combination:

a memory (10) organized

on the one hand, into two spaces, one containing attributes describing the stored data, and the other containing connexity links among the stored data,

and, on the other hand, according to one or more dimensions respectively associated with attributes and divided into one or more hierarchized segments, the data being inputted by creating, deleting or modifying the values of attributes characterizing said segments;

means (11) for integrating one or more incoming information streams which analyze said streams to determine the data constituting same and to structure said data and the attributes thereof according to the organization of said memory (10);

an inference engine (14) implementing, in parallel or in series, inference rules (141) grouped together in libraries (15), said rules (141) being programmed to regenerate a sequence including at least one segment of the memory, by creating, deleting or modifying at least one datum and/or at least one attribute value and/or at least one connexity link during the implementation thereof in the at least one space of the memory,

means (13) for allocating resources activating or deactivating the inference rules (141) on the basis of a priority rule,

means (12) for extracting data, which are identified by programming and/or by at least one selected attribute value and/or at least one selected connexity link; and

/or which are located in one or more selected segments of the memory (10), and providing same in one or more outgoing information streams.

2. Device according to the preceding claim, characterized in that the memory (10) is organized in at least three dimensions, of which at least one time dimension associating with the data one or more attributes making it possible to date the memorization of the data, an idiosyncratic dimension associating with the data one or more attributes making it possible to determine the relative specificity of the data, a conceptual dimension associating with the data one or more attributes making it possible to hierarchize the data according to levels of abstraction (100).

3. Device according to the preceding claim, characterized in that the first space of the memory containing attributes of the data is constituted of even levels (100a) identified as levels of situations, and the second space of the memory containing relations between data is constituted of uneven levels (100b) identified as levels of connexities.

4. Device according to the preceding claim, characterized in that at least one inference rule implemented by the inference engine induces a connexity level of abstraction 2k+1 from a situation level of abstraction 2k and/or a hypersituation level of abstraction 2k+2 from a connexity level of abstraction 2k+1.

5. Device according to one of the preceding claims, characterized in that the priority rule implemented by the means (13) for allocating resources is a function of the hierarchy of the memory segments to be regenerated;

predefined parameters of inference rules (141) and of the interval separating the activation occurrences of the inference rules (141).

6. Device according to one of the preceding claims, characterized in that the memory is connected to a mass storage space in which segments may be saved.

7. Device according to one of the preceding claims, characterized in that the means (12) for extracting data select singular situations, situations having varied, and plausible projected situations.

8. Information-processing system including at least one processing unit, at least one memory unit, a first interface with at least one incoming information stream and a second interface with at least one outgoing information stream, characterized in that it implements the architecture of the processing device according to one of the preceding claims.

9. System according to the preceding claim, characterized in that said processing unit comprises at least one multi-core processor.

10. System according to one of claim 8 or 9, characterized in that said processing unit implements a neuronal network structure.

11. Computer program product including program code instructions which, when they are executed, implement the architecture of the device according to one of claims 1 to 7.