MEMORY SYSTEM

• US 20130179630A1
• Filed: 03/01/2013
• Published: 07/11/2013
• Est. Priority Date: 03/01/2008
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MATSUZAKI, Hidenori, HATSUDA, Kosuke, YANO, Junji
• Granted Patent: US 8,677,059 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data

Abstract

According to one embodiment, a memory system includes a nonvolatile semiconductor memory include a first area, and a second area smaller than the first area; and a controller configured to control data stored in the nonvolatile semiconductor memory, wherein the nonvolatile semiconductor memory is configured to store a first data accessible by a host command and to a second data inaccessible by the host command, and when receiving the host command, the controller writes the second data of the first area within the second area and initializes a first address information related the first data.

Claims

1. A memory system comprising:

a nonvolatile semiconductor memory include a first area, and a second area smaller than the first area; and

a controller configured to control data stored in the nonvolatile semiconductor memory, wherein

the nonvolatile semiconductor memory is configured to store a first data accessible by a host command and to a second data inaccessible by the host command, and

when receiving the host command, the controller writes the second data of the first area within the second area and initializes a first address information related the first data.

2. A memory system comprising:

a nonvolatile semiconductor memory configured to store a management table in which management information including storage positions of data stored in the nonvolatile semiconductor memory is recorded; and

a controller configured to perform data transfer between a host apparatus and the nonvolatile semiconductor memory and to perform management of data stored in the nonvolatile semiconductor memory based on the management table, wherein

the nonvolatile semiconductor memory is configured to store data associated with a first logical addresses accessible from the host apparatus by a first command and to store data associated with a second logical addresses inaccessible from the host apparatus by the first command, and

when receiving the first command from the host apparatus, the controller collects data scattered in a first area, the data being associated with the second logical addresses, by rewriting the data associated with the second logical addresses within a second area of the nonvolatile semiconductor memory and thereafter initializes the management table corresponding to the first logical addresses.

3. The memory system according to claim 2, further comprising a volatile semiconductor memory in communication with the nonvolatile semiconductor memory, wherein

the controller is configured to read out at least one part of the management table into the volatile semiconductor memory and to perform the management of data while updating the management table stored in the volatile semiconductor memory, and

when receiving the first command from the host apparatus, the controller initializes the management table stored in the volatile semiconductor memory and writes the initialized management table in the nonvolatile semiconductor memory.

4. The memory system according to claim 3, wherein the nonvolatile semiconductor memory is configured to store a plurality of management tables,

the plurality of management tables include a first management table that records management information including storage positions of data stored in the volatile semiconductor memory and a second management table that records management information including storage positions of data stored in the nonvolatile semiconductor memory, and

when receiving the first command from the host apparatus, the controller initializes the second management table stored in the volatile semiconductor memory and writes the initialized second management table in the nonvolatile semiconductor memory.

5. The memory system according to claim 4, wherein the controller initializes, when receiving the first command from the host apparatus, a section corresponding to the first logical addresses in the second management table.

6. The memory system according to claim 5, wherein the controller does not initialize, when receiving the first command from the host apparatus, a section corresponding to the second logical addresses in the second management table.

7. The memory system according to claim 2, wherein the controller associates SMART (Self-Monitoring, Analysis and Reporting Technology) information with the second logical addresses.

8. The memory system according to claim 2, wherein the nonvolatile semiconductor memory is a NAND flash memory.

9. The memory system according to claim 2, wherein when receiving the first command from the host apparatus, the controller erases data associated with the first logical addresses in the nonvolatile semiconductor memory.

10. The memory system according to claim 2, wherein the controller determines whether it is necessary to collect data associated with the second logical addresses.

11. The memory system according to claim 2, wherein the volatile semiconductor memory is a DRAM.

12. The memory system according to claim 2, wherein the first command is an erasing command.

13. The memory system according to claim 2, wherein the controller initializes the management table except for a section corresponding to the second logical addresses in the second management table.

14. The memory system according to claim 2, wherein the controller compacts data associated with the second logical addresses by rewriting the data associated with the second logical addresses within the second area of the nonvolatile semiconductor memory to fit in a predetermined number of logical blocks.

15. The memory system according to claim 2, wherein the second area is a predetermined area of the nonvolatile semiconductor memory.

16. The memory system according to claim 2, wherein the second area is a predetermined area of the nonvolatile semiconductor memory.

17. The memory system according to claim 2 further comprising a volatile semiconductor memory, wherein

the management table is preliminarily expanded in the volatile semiconductor memory.

18. The memory system according to claim 17, wherein the volatile semiconductor memory is a DRAM.

19. A memory system comprising:

a nonvolatile semiconductor memory include a first area, and a second area and

a controller configured to control the nonvolatile semiconductor memory, wherein

the first area is accessible by a host command,

the second area is prohibited from being accessed by the host command, and

when a host device sends the host command, the controller performs compaction within the second area and initializes management information.