Dynamically Allocating A Power Budget Over Multiple Domains Of A Processor
First Claim
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1. A processor comprising:
- a first domain and a second domain, each of the first and second domains to operate at an independent voltage and frequency;
a memory controller coupled to the first and second domains;
at least one interface; and
first logic to dynamically allocate a power budget for the processor between the first and second domains at run time.
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Abstract
In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.
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Citations
20 Claims
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1. A processor comprising:
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a first domain and a second domain, each of the first and second domains to operate at an independent voltage and frequency; a memory controller coupled to the first and second domains; at least one interface; and first logic to dynamically allocate a power budget for the processor between the first and second domains at run time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising
determining, in a power controller of a multi-domain processor, a power budget for the multi-domain processor for a current time interval, the multi-domain processor including at least a first domain and a second domain; -
determining, in the power controller, a portion of the power budget to be allocated to the first and second domains; and controlling a frequency of the first domain and a frequency of the second domain based on the allocated portions. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A system comprising:
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a multicore processor having a first domain including a plurality of cores, a second domain including a graphics engine, and a third domain including system agent circuitry, the third domain to operate at a fixed power budget and including a power sharing logic to dynamically allocate a variable power budget between the first and second domains based at least in part on a first power sharing value for the first domain stored in a first storage and a second power sharing value for the second domain stored in a second storage; and a dynamic random access memory (DRAM) coupled to the multicore processor. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification