DECODING IN SOLID STATE MEMORY DEVICES

• US 20130179754A1
• Filed: 09/22/2011
• Published: 07/11/2013
• Est. Priority Date: 09/29/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cherubini, Giovanni, Iliadis, Ilias
• Granted Patent: US 9,176,814 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

In a solid state memory device, codewords stored in a unit of the memory device are decoded using an error correcting iterative decoding process. An average number of iterations needed for successfully decoding codewords of the unit is determined, and the average number of iterations is monitored. The average number of iterations can be taken as a measure of wear of the subject unit.

Claims

1. A method for controlling a solid state memory device, comprising:

decoding codewords stored in a unit of the memory device using an error correcting iterative decoding process,

determining an average number of iterations needed for successfully decoding codewords of the unit, and

monitoring the average number of iterations.

2. A method according to claim 1, wherein subject to the average number of iterations at least one of the following activities is triggered:

modifying a mode the unit is operated in;

applying a wear-levelling routine;

no longer operating the unit;

preventing loss of data with respect to the unit;

modifying one or more parameters used in the decoding process, and continue running the decoding process with the modified parameters.

3. A method according to claim 1,

wherein the monitoring of the average number of iterations includes comparing the average number of iterations to a threshold, and

wherein at least one activity is triggered when the average number of iterations exceeds the threshold.

4. A method according to claim 3, wherein the unit is marked when the average number of iterations exceeds the threshold.

5. A method according to claim 3,

wherein one of a maximum latency and a maximum number of iterations is defined after which the decoding process for decoding a codeword is terminated at latest, and

wherein the maximum latency or the maximum number of iterations respectively is increased when the average number of iterations exceeds the threshold.

6. A method according to claim 1,

wherein a maximum user bit error rate is defined with the user bit error rate being the error bit rate of codewords after having applied the error correcting iterative decoding process,

and wherein the maximum user bit error rate is increased when the average number of iterations increases.

7. A method according to claim 1, wherein in the decoding process a number of quantization levels is applied in iterations for determining an a posteriori probability of a code symbol binary value represented by a physical value stored in a cell of the memory device which number of quantization levels exceeds the number of code symbols available per cell.

8. A method according to claim 1, wherein the average number of iterations of a unit is determined by accumulating the number of iterations needed for successfully decoding codewords of a unit for a predetermined number of readings from the unit and by dividing the accumulated number of iterations by the predetermined number of readings.

9. A method according to claim 8, wherein the time needed for the predetermined number of readings is monitored.

10. A method according to claim 1,

wherein the memory device comprises multiple units,

wherein the average number of iterations is determined for each unit, and

wherein an average number of iterations for the device is determined by accumulating the average number of iterations of each of the units and by dividing the accumulated average number by the number of the units.

11. A method according to claim 1, wherein the device comprises a single unit.

12. A computer program product comprising a computer readable medium having computer readable program code embodied therewith, the computer readable program code comprising computer readable program code configured to perform a method according to claim 1.

13. A for controlling a solid state memory device, comprising:

a decoder configured to decode codewords stored in a unit of the memory device using an error correcting iterative decoding process,

a computing unit configured to determine an average number of iterations needed for successfully decoding codewords of the unit, and

a monitoring unit configured to monitor the average number of iteration.

14. A controller according to claim 13, wherein the decoder includes multiple decoding units configured to decode multiple codewords stored in the unit of the memory device in parallel each by using an error correcting iterative decoding process.

15. A controller according to claim 13,

wherein the decoder includes a single decoding unit configured to decode a codeword stored in the unit of the memory device using an error correcting iterative decoding process, and

wherein a queue is configured to store consecutive codewords to be decoded by the decoder.

16. A memory device comprising a solid state memory and a storage controller according to claim 13 for controlling the solid state memory.