INTEGRATION OF CURRENT BLOCKING LAYER AND n-GaN CONTACT DOPING BY IMPLANTATION

• US 20130181186A1
• Filed: 01/16/2012
• Published: 07/18/2013
• Est. Priority Date: 01/16/2012
• Status: Active Grant

• Current Assignee: Varian Semiconductor Equipment Associates Incorporated (Applied Materials Incorporated)
• Original Assignee: Varian Semiconductor Equipment Associates Incorporated (Applied Materials Incorporated)
• Inventors: Chen, Chi-Chun, Jiang, Tao
• Granted Patent: US 8,603,847 B2
• Time in Patent Office: Days
• US Class Current: 257/13
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/14 with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
• CPC Class Codes: H01L 33/145 with a current-blocking structure
• CPC Class Codes: H01L 33/32 containing nitrogen

Abstract

An improved method of fabricating a semiconductor light emitting diode (LED) is disclosed. The current blocking layer and the contact area for the n-type layer are implanted at the same time. In some embodiments, a dopant, which may be an n-type dopant, is implanted into a portion of the p-type layer to cause that portion to become either u-type or n-type. Simultaneously, the same dopant is implanted into at least a portion of the exposed n-type layer to increase its conductivity. After this implant, the dopant in both portions of the LED may be activated through the use of a single anneal cycle.

Claims

1. A method of fabricating a light emitting diode (LED), comprising:

creating a structure having a n-type layer, a multi-quantum well (MQW) on said n-type layer, and a p-type layer on said MQW, where a portion of said n-type layer is exposed;

simultaneously selectively implanting ions into a first region of said p-type layer to reduce conductivity in said first region and into a second region of said n-type layer to increase conductivity in said second region;

applying a p electrode to said p-type layer; and

applying an n electrode to said portion of said n-type layer.

2. The method of claim 1, wherein said ions comprise an n-type dopant.

3. The method of claim 2, wherein said ions comprise silicon.

4. The method of claim 1, wherein said creating step comprises:

growing said n-type layer on a substrate;

growing said MQW on said n-type layer;

growing said p-type layer on said MQW;

disposing a mask on said p-type layer that defines an opening configured to leave a portion of said p-type layer exposed;

performing an etching process of said portion of said p-type layer, such that said portion of said p-type layer and said MQW beneath said portion of said p-type layer are removed, thereby exposing said portion of said n-type layer.

5. The method of claim 1, wherein said LED comprises a vertical sidewall, and said method further comprises disposing a mask on said vertical sidewall prior to said selective implanting.

6. The method of claim 1, further comprising depositing a transparent coating layer on a top surface of said LED prior to applying said p electrode and said n electrode.

7. The method of claim 1, further comprising performing an anneal cycle after said selectively implanting said ions into said first region and said second region.

8. A light emitting diode, comprising:

a structure having a n-type layer, a multi-quantum well (MQW) on said n-type layer, and a p-type layer on said MQW, where a portion of said n-type layer is exposed;

a p electrode on said p-type layer;

an n electrode on said portion of said n-type layer;

a region of reduced conductivity disposed in said p-type layer beneath said p electrode; and

a region of increased conductivity disposed in said portion of said n-type layer beneath said n electrode;

wherein said region of reduced conductivity and said region of increased conductivity both comprise one species of implanted ions.

9. The light emitting diode of claim 8, wherein said one species comprises silicon.

10. The light emitting diode of claim 8, further comprising a transparent coating layer disposed on a top surface of said light emitting diode beneath said p electrode and said n electrode.

11. A light emitting diode made by a process comprising:

creating a structure having a n-type layer, a multi-quantum well (MQW) on said n-type layer, and a p-type layer on said MQW, where a portion of said n-type layer is exposed;

simultaneously selectively implanting ions into a first region of said p-type layer to reduce conductivity in said first region and into a second region of said n-type layer to increase conductivity in said second region;

applying a p electrode to said p-type layer; and

applying an n electrode to said portion of said n-type layer.

12. The light emitting diode of claim 11, wherein said ions comprise an n-type dopant.

13. The light emitting diode of claim 12, wherein said ions comprise silicon.

14. The light emitting diode of claim 11, wherein said creating step comprises:

growing said n-type layer on a substrate;

growing said MQW on said n-type layer;

growing said p-type layer on said MQW;

disposing a mask on said p-type layer that defines an opening configured to leave a portion of said p-type layer exposed;

performing an etching process of said portion of said p-type layer, such that said portion of said p-type layer and said MQW beneath said portion of said p-type layer are removed, thereby exposing said portion of said n-type layer.

15. The light emitting diode of claim 11, wherein said LED comprises a vertical sidewall, and said process further comprises disposing a mask on said vertical sidewall prior to said selective implanting.

16. The light emitting diode of claim 11, wherein said process further comprises depositing a transparent coating layer on a top surface of said light emitting diode prior to applying said p electrode and said n electrode.

17. The light emitting diode of claim 11, wherein said process further comprises performing an anneal cycle after said selectively implanting said ions into said first region and said second region.