SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

• US 20130181212A1
• Filed: 07/06/2012
• Published: 07/18/2013
• Est. Priority Date: 01/17/2012
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Byung Du Ahn, Gun Hee Kim, Jae Woo Park, Je-Hun Lee, Ji Hun Lim, Jin Hyun Park, Jung Hwa Kim, Jun Hyun Park, Kyoung Won Lee, Sei-Yong Park, Yeon Hong Kim
• Inventors: KIM, Gun Hee, PARK, Jae Woo, AHN, Byung Du, LEE, Je Hun, PARK, Sei-Yong, LIM, Ji Hun, PARK, Jin Hyun, KIM, Yeon Hong, KIM, Jung Hwa, PARK, Jun Hyun, LEE, Kyoung Won
• Granted Patent: US 9,070,777 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A semiconductor device includes: a substrate, a semiconductor layer including an oxide semiconductor disposed on the substrate, a barrier layer disposed on the semiconductor layer and an insulating layer disposed on the barrier layer. The semiconductor layer includes an oxide semiconductor, and the barrier layer includes a material having a lower standard electrode potential than a semiconductor material of the oxide semiconductor, a lower electron affinity than the semiconductor material of the oxide semiconductor, or a larger band gap than the semiconductor material of the oxide semiconductor. The insulating layer includes at least one of a silicon-based oxide or a silicon-based nitride, and the insulating layer includes a portion which contacts with an upper surface of the barrier layer.

Claims

1. A semiconductor device comprising:

a substrate;

a semiconductor layer disposed on the substrate;

a barrier layer disposed on the semiconductor layer; and

an insulating layer disposed on the barrier layer,

wherein the semiconductor layer includes an oxide semiconductor,

wherein the barrier layer includes a material including at least one of a lower standard electrode potential than a semiconductor material of the oxide semiconductor, a lower electron affinity than the semiconductor material of the oxide semiconductor, or a larger band gap than the semiconductor material of the oxide semiconductor,

wherein the insulating layer includes at least one of a silicon-based oxide or a silicon-based nitride, and

wherein the insulating layer includes a portion which contacts with an upper surface of the barrier layer.

2. The semiconductor device of claim 1, wherein

the oxide semiconductor includes at least one of indium (In), gallium (Ga), zinc (Zn), or tin (Sn).

3. The semiconductor device of claim 2, wherein

the barrier layer includes an oxide including at least one selected from a group including aluminum, gallium, yttrium, niobium, silicon, magnesium, hafnium, titanium, lanthanum, lithium, scandium, barium, strontium, or zirconium.

4. The semiconductor device of claim 1, wherein

the semiconductor layer includes an indium oxide, a zinc oxide, and a tin oxide, and wherein the barrier layer includes a gallium oxide, an indium oxide, and a zinc oxide.

5. The semiconductor device of claim 1, further comprising:

a gate insulating layer disposed on the substrate;

a gate electrode disposed on the gate insulating layer; and

a source electrode and a drain electrode disposed between the barrier layer and the insulating layer,

wherein the source electrode and the drain electrode are separated from each other, and wherein the barrier layer and the insulating layer contact each other in a space between the source electrode and the drain electrode.

6. The semiconductor device of claim 1, further comprising:

a gate insulating layer disposed on the substrate;

a gate electrode disposed on the gate insulating layer;

a source electrode and a drain electrode disposed between the barrier layer and the insulating layer, wherein the source electrode and the drain electrode are separated from each other; and

a passivation layer disposed on the source electrode and the drain electrode and wherein the passivation layer contacts with the barrier layer in a space between the source electrode and the drain electrode.

7. The semiconductor device of claim 1, further comprising:

a gate electrode disposed on the insulating layer;

an interlayer insulating layer disposed on the gate electrode and including a contact hole; and

a source electrode and a drain electrode disposed on the interlayer insulating layer and connected to the semiconductor layer through the contact hole.

8. The semiconductor device of claim 1, wherein

the insulating layer includes at least one of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

9. A method of forming a semiconductor device, comprising;

forming a semiconductor layer on a substrate;

forming a barrier layer on the semiconductor layer; and

forming an insulating layer on the barrier layer by using a deposition method using plasma,

wherein the semiconductor layer includes an oxide semiconductor,

wherein the barrier layer includes a material including at least one of a lower standard electrode potential than a semiconductor material of the oxide semiconductor, a lower electron affinity than the semiconductor material of oxide semiconductor, or a larger band gap than the semiconductor material of the oxide semiconductor,

wherein the insulating layer includes at least one of a silicon-based oxide or a silicon-based nitride, and

wherein the insulating layer includes a portion which contacts with an upper surface of the barrier layer.

10. The method of claim 9, wherein

the oxide semiconductor includes at least one of indium (In), gallium (Ga), zinc (Zn), or tin (Sn).

11. The method of claim 10, wherein

the barrier layer includes an oxide including at least one selected from a group including aluminum, gallium, yttrium, niobium, silicon, magnesium, hafnium, titanium, lanthanum, lithium, scandium, barium, strontium, or zirconium.

12. The method of claim 9, wherein

the semiconductor layer includes an indium oxide, a zinc oxide, and a tin oxide, and wherein the barrier layer includes a gallium oxide, an indium oxide, and a zinc oxide.

13. The method of claim 9, further comprising:

forming a gate insulating layer on the substrate;

forming a gate electrode on the gate insulating layer; and

forming a source electrode and a drain electrode between the barrier layer and the insulating layer,

wherein the source electrode and the drain electrode are separated from each other, and wherein the barrier layer and the insulating layer contact each other in a space between the source electrode and the drain electrode.

14. The method of claim 9, further comprising:

forming a gate insulating layer on the substrate;

forming a gate electrode on the gate insulating layer;

forming a source electrode and a drain electrode between the barrier layer and the insulating layer and wherein the source electrode and the drain electrode are separated from each other; and

forming a passivation layer on the source electrode and the drain electrode and wherein the passivation layer contacts with the barrier layer in a space between the source electrode and the drain electrode.

15. The method of claim 9, further comprising

forming a gate electrode on the insulating layer;

forming an interlayer insulating layer including a contact hole on the gate electrode; and

forming a source electrode and a drain electrode connected to the semiconductor layer through the contact hole on the interlayer insulating layer.

16. The method of claim 9, wherein

the insulating layer includes at least one of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiONx).

17. A method of forming a semiconductor device, comprising;

forming a gate electrode on a substrate;

forming a gate insulating layer on the gate electrode;

forming a semiconductor layer on the gate insulating layer, wherein the semiconductor layer includes an oxide semiconductor;

forming a barrier layer on the semiconductor layer, wherein the barrier layer includes a material including at least one of a lower standard electrode potential than a semiconductor material of the oxide semiconductor, a lower electron affinity than the semiconductor material of the oxide semiconductor, or a larger band gap than the semiconductor material of the oxide semiconductor;

forming an insulating layer on the barrier layer by using a deposition method using plasma, wherein the insulating layer includes at least one of a silicon-based oxide or a silicon-based nitride;

forming an etch stopper on the barrier layer;

forming a source electrode and a drain electrode spaced apart from the source electrode on the barrier layer;

forming a passivation layer on the source electrode and the drain electrode and wherein the passivation layer contacts with the etch stopper in a space between the source electrode and the drain electrode.

18. The method of claim 17, wherein

the oxide semiconductor includes at least one of indium (In), gallium (Ga), zinc (Zn), or tin (Sn).

19. The method of claim 18, wherein

the barrier layer includes an oxide including at least one selected from a group including aluminum, gallium, yttrium, niobium, silicon, magnesium, hafnium, titanium, lanthanum, lithium, scandium, barium, strontium, or zirconium.

20. The method of claim 17, wherein the semiconductor layer includes indium-zinc-tin oxide and wherein the barrier layer includes indium-gallium-zinc oxide.