SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20130181221A1
• Filed: 12/10/2012
• Published: 07/18/2013
• Est. Priority Date: 01/17/2012
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: KANEKO, Kishou, SUNAMURA, Hiroshi, HAYASHI, Yoshihiro
• Granted Patent: US 9,496,403 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/00 Logic circuits, i.e. having at least two inputs acting on one output circuits for computer systems using fuzzy logic G06N7/02; Inverting circuits

Abstract

A circuit including an inverter is provided for a wiring layer.

A semiconductor device is provided with a wiring layer circuit which is formed over an insulating film and includes at least one inverter element. The inverter is provided with a first transistor element and a resistance element which is connected to the first transistor via a connection node. The first transistor element is provided with a gate electrode which is embedded in an interlayer insulating film including the insulating film, a gate insulating film which is formed over the interlayer insulating film and the gate electrode, and a first semiconductor layer which is formed over the gate insulating film between a source electrode and a drain electrode. The resistance element is provided with a second semiconductor layer which functions as a resistance. The first semiconductor layer and the second semiconductor layer are formed in the same layer.

Claims

1. A semiconductor device including a wiring layer circuit which is formed over an insulating film and includes at least one inverter element, the inverter element comprising:

a first transistor element; and

a resistance element connected to the first transistor element via a connection node,

the first transistor element including;

a gate electrode embedded in an interlayer insulating film which includes the insulating film;

a gate insulating film formed over the interlayer insulating film and the gate electrode; and

a first semiconductor layer formed over the gate insulating film between a source electrode and a drain electrode, and

the resistance element including,

a second semiconductor layer functioning as a resistance,

wherein the first semiconductor layer and the second semiconductor layer are formed in the same layer.

2. The semiconductor device according to claim 1,

wherein each of the first semiconductor layer and the second semiconductor layer is an oxide semiconductor layer.

3. The semiconductor device according to claim 1, further comprising:

a semiconductor substrate; and

a foundation layer logic circuit part formed over the semiconductor substrate, the part including;

an active element; and

a plurality of wiring layers formed above the active element,

wherein the insulating film is formed over the wiring layers.

4. The semiconductor device according to claim 3,

wherein the active element in the foundation layer logic circuit is connected to the first transistor of the inverter element in the wiring layer circuit.

5. The semiconductor device according to claim 1,

wherein the inverter element further includes a second transistor which is connected to the first transistor in series between the first transistor and a ground voltage, and

the resistance element is connected to a power source voltage, and

wherein the second transistor includes:

a second gate electrode which is embedded in the interlayer insulating film including the insulating film;

a second gate insulating film which is formed over the interlayer insulating film and the second gate electrode; and

a third semiconductor layer which is formed over the second gate insulating film between a source electrode and a drain electrode.

6. The semiconductor device according to claim 1,

wherein the inverter element further includes a second transistor which is connected to the first transistor in parallel between the resistance element and a ground voltage,

the resistance element is connected to a power source voltage, and

the first transistor is connected to the ground voltage, and

wherein the second transistor element includes;

a second gate electrode which is embedded in the interlayer insulating film including the insulating film;

a second gate insulating film which is formed over the interlayer insulating film and the second gate electrode; and

a third semiconductor layer which is formed over the second gate insulating film between a source electrode and a drain electrode.

7. The semiconductor device according to claim 1,

wherein the resistance element includes;

an adjustment electrode which is embedded in the interlayer insulating film including the insulating film;

an adjustment insulating film which is formed over the interlayer insulating film; and

a fourth semiconductor layer which is formed over the adjustment insulating film, and

wherein a resistance value of the resistance element is adjusted according to a voltage applied to the adjustment electrode.

8. The semiconductor device according to claim 5,

wherein the resistance element includes:

an adjustment electrode which is embedded in the interlayer insulating film including the insulating film;

an adjustment insulating film which is formed over the interlayer insulating film; and

a fourth semiconductor layer which is formed over the adjustment insulating film, and

wherein the adjustment electrode is connected to the drain electrode of the first transistor.

9. The semiconductor device according to claim 1,

wherein the wiring layer circuit includes an odd number of the inverter elements which are connected in a chain shape.

10. The semiconductor device according to claim 9,

wherein the resistance element includes;

an adjustment electrode which is embedded in the interlayer insulating film including the insulating film;

an adjustment insulating film which is formed over the interlayer insulating film; and

a fourth semiconductor layer which is formed over the adjustment insulating film, and

wherein a resistance value of the resistance element is adjusted according to a voltage applied to the adjustment electrode.

11. The semiconductor device according to claim 10,

wherein the adjustment electrodes of the odd number of inverters which are connected in the chain shape are set to have the same predetermined voltage.

12. The semiconductor device according to claim 1,

wherein the first semiconductor layer and the second semiconductor layer are formed in an integrated manner.

13. The semiconductor device according to claim 1,

wherein the first semiconductor layer and the second semiconductor layer are formed to be different patterns.

14. A manufacturing method of a semiconductor device, comprising the steps of:

forming a gate electrode which is embedded in an interlayer insulating film including an insulating layer;

forming a gate insulating film over the interlayer insulating film and the gate electrode; and

forming a semiconductor layer over the gate insulating film so as to cover the gate electrode in a transistor region via the gate insulating film.

15. The manufacturing method of a semiconductor device according to claim 14,

wherein the semiconductor device has a transistor structure in which a part corresponding to the gate electrode in the semiconductor layer functions as a source electrode or a drain electrode,

the step of forming the gate electrode includes forming of an adjustment electrode which is embedded in the interlayer insulating film in a load resistance region, and

the semiconductor device has a transistor structure in a part corresponding to the adjustment electrode in the semiconductor layer, and

wherein a resistance value of the resistance element is adjusted according to a voltage applied to the adjustment electrode.